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DepTyCheck / verilog-model Public

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Procedural blocks and expressions#85

Draft

GlebChili wants to merge 5 commits intomasterDepTyCheck/verilog-model:masterfrom

always-blocksDepTyCheck/verilog-model:always-blocksCopy head branch name to clipboard

Conversation Commits5 (5)Checks Files changed

Draft

Procedural blocks and expressions#85
GlebChili wants to merge 5 commits intomasterfrom
always-blocks

Commits

Commits on May 12, 2025

Trivial SystemVerilog Expressions added
GlebChili
committed
Remove redundant DecEq definition
GlebChili
committed
Remove redundant DecEq defintion
GlebChili
committed
Add binary, unary, and ternary operators to expressions
GlebChili
committed
Added ProceduralBlocks
GlebChili
committed

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