High-performance functional simulator for ASIC architecture validation, designed for Cisco Silicon One unified silicon architecture specifications.
This framework implements functional simulators for web-scale and service provider network switching/routing ASICs. The C/C++ core provides hardware-accurate packet processing models while Python handles automation, validation, and performance monitoring.
┌─────────────────────────────────────────┐
│ Simulation Runner (Python) │
├─────────────────────────────────────────┤
│ Model Validator (Python) │
├─────────────────────────────────────────┤
│ Simulator Core (C) │
├─────────────────────────────────────────┤
│ Packet Processor (C++) │
│ ┌──────────┬──────────┬────────────┐ │
│ │ L2 Model │ L3 Model │ P4 Model │ │
│ └──────────┴──────────┴────────────┘ │
└─────────────────────────────────────────┘
- Simulator core in C for hardware-accurate cycle simulation
- C++ packet processor with L2 switching, L3 routing, P4 pipeline
- Python automation for simulation orchestration and reporting
- Configurable via YAML for different architecture specifications
- Full test suite with PyTest
| Layer | Technology |
|---|---|
| Core Simulator | C |
| Packet Processing | C++ |
| Automation | Python |
| Testing | PyTest, GDB |
| Config | YAML |
| CI/CD | GitHub Actions |
# Compile C core
gcc -o bin/simulator src/simulator_core.c
# Compile C++ packet processor
g++ -std=c++17 -o bin/packet_processor \
src/packet_processor.cpp
# Install Python dependencies
pip install pyyaml pytest
# Run simulation
python scripts/run_simulation.py
# Run tests
pytest tests/| Metric | Value |
|---|---|
| L2 Latency | 100ns |
| L3 Latency | 150ns |
| P4 Latency | 200ns |
| Max Throughput | 10M pkts/sec |
| Test Coverage | 90%+ |