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class HarshaVardhan:
def __init__(self):
self.name = "Harsha Vardhan"
self.university = "KL University"
self.degree = "B.Tech ECE"
self.focus = ["VLSI Design", "ASIC", "Semiconductors"]
self.languages = ["Python", "C", "Verilog"]
self.tools = ["Cadence", "Synopsys", "Digital Design Flow"]
self.exploring = "ML + Hardware Integration"
self.goal = "Build at the intersection of Hardware & AI 🚀"
def current_status(self):
return "Turning silicon into intelligence ⚡"
| 🔹 Domain | 🛠️ Tools / Skills |
|---|---|
| VLSI & Digital Design | Cadence, Synopsys, Verilog HDL |
| Embedded Systems | ESP32, Sensors, IoT Protocols |
| Machine Learning | Python, NumPy, Scikit-learn |
| Web Development | React, Vite, Tailwind CSS |
| Circuit Design | Analog + Digital Electronics |
|
Real-time weather application with live API integration. Fetches live data, displays forecasts with a clean interface. → Python · Web APIs · Data Parsing |
Smart attention monitoring system using sensors + ESP32. Bridges embedded systems with real-world intelligence. → IoT · Embedded C · Sensors |
Fully responsive personal portfolio built with React + Vite + Tailwind. Live on Vercel. → React · Vite · Tailwind CSS |
[ ✅ ] Build a strong academic resource repo
[ ✅ ] Launch personal portfolio
[ 🔄 ] Master Cadence & Synopsys digital design flow
[ 🔄 ] Complete VLSI project from RTL → GDSII
[ ⏳ ] Publish research / technical blog
[ ⏳ ] Open-source an ML + Hardware project
[ ⏳ ] Land VLSI / Semiconductor internship
