Modern Amiga 1200 clone implementation using Cyclone V FPGA
The hardware design supports these features:
USB-C PD Sink / TCPC
USB-C DP Sink (4-lane Alt Mode)
DisplayPort Output
DisplayPort Retimer
USB-C 2.0 End point / Hub
USB Keyboard
USB Mouse
UART to FPGA Debug port
UART to ESP32 Programming port / bootstrap
KVM to switch Monitor/Keyboard/mouse between USB-C upstream or FPGA USB OTG
DVI-A output
ESP32 as the embedded controller
KVM Switch control
Fan Speed Control
A500 Keyboard scanner
USB HID
VGA (64 color) display for boot time messages
RTC Emulation on I2C
SLiRP Modem Emulation on UART
FPGA I2S to analog 3.5mm audio jack output
DDR RAM to FPGA expansion bus
Cyclone V FPGA on the draughtboard
Hardware Pin assignments:
EC (ESP32) Functions and pin assignments
@o: output
@i: Input
3v3: +3.3V logic
1v8: +1.8V logic
Boot strap (flash): IO0@i, EN@i, U0RXD@i3v3, U0TXD@o3v3
TCPC
Negotiate SINK 5V@3A + 4-lane DP Alt Mode
I2C Controller: IO21/SDA, IO38/SCL
DVI-A/VGA output:
Red[0,1] = [IO10,IO11]@o3v3
Green[0,1] = [IO40,IO45]@o3v3
Blue[0,1] = [IO39,IO46]@o3v3
HSYNC = IO47@o1v8
VSYNC = IO48@o1v8
DDR
Power Good: IO2@o3v3
I2C same pin as controller
WiFi SLiRP modem, UART1
TxD = U1TXD@o3v3
RxD = U1RXD@i3v3
KVM
User Switch: IO3@i falling edge
Port selection: IO5@o3v3, L = USBC DP, H = FPGA DP
FPGA
Temp sensor interupt alaram IO4@i3v3 falling edge
Cooling Fan: SENS = IO7@i3v3, PWM = IO8@o3v3
I2C peripheral: IO41/SCL, IO42/SDA
Expansion port:
A500 Keyboard:
CLK = IO12@o3v3
DATA = IO13@i3v3
RST = IO14@o3v3
LED STATUS = IO15@o3v3
LED INUSE = IO16@o3v3
FPGA (Cyclone V) Functions and pin assignments
Net
FPGA Pin
DP0-
AD11
DP0+
AD10
DP1-
AH5
DP1+
AH6
AUX-
AE7
AUX+
AF6
HPD
AF11
Net
FPGA Pin
DP0-
AA15
DP0+
Y15
DP1-
AF28
DP1+
AF27
DP2-
AH27
DP2+
AG28
AUX-
AD26
AUX+
AE25
HPD
AC24
LP
AG26
Net
FPGA Pin
D0+
AG25
D0-
AF25
D1+
AH24
D1-
AG24
D2+
AG23
D2-
AF23
CK+
AH23
CK-
AH22
HPD
AG21
Pin
FPGA Pin
1
AH9
2
AG11
3
AF15
4
AH11
5
AH12
6
AG16
7
AF17
8
AD4
Net
FPGA Pin
DIN
AC4
LRCK
AG8
BCK
AG10
MUTE
AH8
Net
FPGA Pin
RXD
U9
TXD
V10
Net
FPGA Pin
SDA
AG9
SCK
U14
Net
FPGA Pin
OSD
AF13
RST
AG13
USER
U13
Net
FPGA Pin
PWR
AA23
USR
AE26
DSK
Y16
Some sections of the hardware design were inspired by the following projects.
The hardware files in this repository are released under Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)