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🤗 Hugging Face Dataset | 🤗 Hugging Face Model | 🌐 ModelScope Dataset | 🌐 ModelScope Model | 📄 Paper
ReasoningV is a novel model designed to enhance Verilog code generation by addressing key challenges faced by Large Language Models (LLMs), including data quality limitations, insufficient reasoning capabilities for complex hardware tasks, and computational inefficiency. We propose a hybrid reasoning strategy that integrates trained intrinsic capabilities with dynamic inference adaptation.
Our work introduces three complementary innovations:
- ReasoningV Dataset: A high-quality dataset of functionally verified Verilog instances with reasoning paths.
- Two-Stage Training: A training approach combining parameter-efficient fine-tuning for foundational knowledge with full-parameter optimization for enhanced reasoning.
- Adaptive Reasoning Mechanism: Dynamically adjusts reasoning depth based on problem complexity to improve efficiency (reducing token consumption) while preserving performance.
Experimental results demonstrate ReasoningV's effectiveness, achieving competitive performance on Verilog benchmarks compared to leading models, particularly standing out among open-source alternatives. This work aims to provide a more reliable and accessible pathway for advancing AI-driven hardware design automation.
We are committed to open-sourcing the key components of the ReasoningV project to facilitate research and development in AI-driven hardware design.
We have released the following resources:
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✅ ReasoningV Dataset: High-quality, functionally verified dataset available on:
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✅ ReasoningV-7B Model Weights: Pre-trained model weights available on:
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Two-Stage Training Code: Code implementation for our proposed training methodology.
Release Strategy:
The dataset and model weights are now available on both Hugging Face and ModelScope platforms. We will continue to release the training code and other associated resources sequentially after the paper is formally accepted for publication. Stay tuned for updates!
If you find ReasoningV useful for your research, please consider citing our paper:
@article{qin2025reasoningv,
title={ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model},
author={Qin, Haiyan and Xie, Zhiwei and Li, Jingjing and Li, LiangChen and Feng, Xiaotong and Liu, Junzhan and Kang, Wang},
journal={arXiv preprint arXiv:2504.14560},
year={2025}
}This project is licensed under the Apache License 2.0 - see the LICENSE file for details.