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svenpeter42
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Feb 6, 2026
proxyclient/tools/chainload.py
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| continue | ||
| if val & 1: | ||
| print(f"{hex(val & 0xfffffffff000)} != {hex(rvbar)}") | ||
| print("The cpu_impl_reg is already locked, this might fail...") |
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I'd just throw an exception here or even check for this earlier and refuse to even start.
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| write64(impl, (u64)_vectors_start); | ||
| if ((read64(impl) & 0xfffffffff000) != (u64)_vectors_start) { | ||
| write64(impl, (u64)_vectors_start); |
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Same here, if the register is locked and doesn't contain the right address just fail earlier
Signed-off-by: Yureka <yureka@cyberchaos.dev>
svenpeter42
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Feb 6, 2026
proxyclient/tools/chainload.py
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| if locked and do_write: | ||
| raise Exception("RVBAR is locked and does not already contain start address") | ||
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| if write_rvbar: |
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How can this even work? write_rvbar isn't defined anywhere before. Please fix and test this before pushing.
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Now compile-tested. I'll be a while before I can test on my M4 again.
Signed-off-by: Yureka <yureka@cyberchaos.dev>
Signed-off-by: Yureka <yureka@cyberchaos.dev>
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According to the discussion here, the RVBAR at cpu_impl_reg+0x00 is already set to the m1n1 entrypoint and locked by iBoot for all cores on M4.
Indeed, I can see the following values:
m1n1 base:
0x100034f4000E-Cores cpu_impl_reg at
0x210X50000:0x100100034f4001P-Cores cpu_impl_reg at
0x211X50000:0x1100100034f4001And voila, when skipping the writes when the value is already correct (which previously produced SErrors when writing to the P-Core cpu_impl_reg),
smp_start_secondaries()now works as expected.