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1. Bilinear_Interpolation Bilinear_Interpolation Public

   Bilinear Image Scaling Accelerator (RTL): Implemented a Verilog-based fixed-point bilinear interpolation engine to resize images. Designed coordinate mapping, neighbor pixel selection, and weighted…

   Verilog 1

2. Digisim_ps1 Digisim_ps1 Public

   Digital hardware design that reads up to 7 coordinate points from ROM, stores them in registers, selects point pairs using counters and multiplexers, computes distance and a custom metric, and cont…

3. FFT_IN_FPGA FFT_IN_FPGA Public

   Real-time 2D FFT edge detection accelerator on Zynq-7000, featuring a memory-efficient Radix-2 SDF architecture and zero-latency Ping-Pong buffering.

   Verilog

4. AES-128 AES-128 Public

   A high-speed, fully pipelined AES-128 cryptographic hardware accelerator for the Xilinx Zynq-7000 SoC, featuring a custom AXI4-Lite Slave Memory interface and bare-metal C driver.

   Verilog

5. Single_Cycle_RISCV_Processor Single_Cycle_RISCV_Processor Public

   A 32-bit Single-Cycle RISC-V (RV32I) Processor designed from scratch in Verilog HDL. Features a custom datapath, control unit, and Harvard memory architecture, fully simulated and verified in Xilin…

   Verilog

6. CAN_Protocol CAN_Protocol Public

   LTspice simulation and mitigation of severe EMI on an EV CAN bus. Compares Shielded Cable and RC Low-Pass Filter approaches to suppress 100V motor transients, achieving <100mV common-mode noise and…