🔭 I’m currently working on hardware-aware performance optimization for a final year/project initiative, bridging architectural decisions around memory, parallelism, and power to deliver real-world speedups. I’m applying RTL design and verification (SystemVerilog) experience to practical, high-performance computing problems, with hands-on use of industry-standard toolchains (Quartus, ModelSim, Icarus Verilog).
👯 I’m looking to collaborate on ASIC design, systems/HPC engineering, and computer architecture projects that require cross-domain thinking between hardware and software. I’m eager to partner with teams focused on performance reasoning, optimization across hardware/software boundaries, and multi-disciplinary problem solving in heterogeneous and parallel environments.
🤝 I’m looking for help with guidance on shaping a final project around hardware-aware performance optimization, exposure to entry-level roles in ASIC design and HPC engineering, and opportunities to strengthen proficiency in C++ performance-oriented development in hardware-aware contexts. Feedback on architecture choices, testing strategies, and performance measurement techniques would be especially valuable.
🌱 I’m currently learning advanced topics in computer architecture, memory hierarchy design, and power-aware optimization techniques. I’m deepening skills in HDL-based design (SystemVerilog), and expanding my software toolkit for high-performance systems in C++ to better reason about cross-domain tradeoffs.
💬 Ask me about how architectural decisions around memory, parallelism, and power translate into real-world speedups; examples of RTL design and verification workflows; experiences with toolchains like Quartus, ModelSim, and Icarus Verilog; and projects where hardware-software co-design yielded measurable performance gains.
⚡ Fun fact: I enjoy translating hardware constraints into elegant performance narratives—think “meet the power budget, beat the latency,” with a dash of hardware-software collaboration storytelling.
