Architecture Progress

[AdaMahdavi]

todo:

PL:

• DSP48E2 cascade with PCIN/PCOUT hardwired accumulation
• Data dependency hazard handling via input queue shift registers
• BRAM/URAM memory hierarchy and control FSM
• Timing closure at 400MHz (Pblock constraints, implementation)
• Full PL datapath simulation against NumPy reference

PS-PL:

• AXI-Lite control interface
• DMA for streaming activations and weights from PS DDR
• Hardware bringup for end-to-end test on KV260