arm64: dts: aspeed: configure SCU1 uart-clk-source#281
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| #size-cells = <2>; | ||
| #clock-cells = <1>; | ||
| #reset-cells = <1>; | ||
| uart-clk-source = <0xff0>; /* bit[x]: 0 uxclk, 1 huxclk */ |
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@rajaganeshr a question: as per this bit mask UART0 - UART3 are still sourced with clock from UXCLK, and UART 4 - to UART are sourced with clock from HUXCLK for higher baud rates. Which UART did you use to verify the HUXCLK, and which baudrate did you use?. this is for my understanding. thank you.
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To use high baud rate ( > 115200bps), we must use HUXCLK as clock source.
Tested ttyS13 ( P0 UART) upto 948k (~1M). Baud rate above that require LTPI freq greater than 100Mhz.
realized now that ttyS3 also needs HUXCLK (P1 UART), will refresh this submission to use HUXCLK for all UARTs.
Add uart-clk-source to the AST2700 SCU1 syscon node. UART defaults to UXCLK (supports up to 115200 baud). For high-speed UART (>115200), UART clock source must switch to HUXCLK. The uart-clk-source bitfield controls this per UARTx (LSB-first), so set it to <0xfff> for all instances. Tested: Verified on kenya. uart-clk-source is present under syscon1:syscon@14c02000 with value <0xff0>. Signed-off-by: Rajaganesh Rathinasabapathi <Rajaganesh.Rathinasabapathi@amd.com>
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Add uart-clk-source to the AST2700 SCU1 syscon node.
UART defaults to UXCLK (supports up to 115200 baud). For high-speed UART (>115200), UART clock source must switch to HUXCLK.
The uart-clk-source bitfield controls this per UARTx (LSB-first), so set it to <0xff0> for the required high-speed UART instances.
Tested: Verified on kenya. uart-clk-source is present under syscon1:syscon@14c02000 with value <0xff0>.