[Do Not Merge] intel18A

Viewer/index.html

@@ -151,7 +151,7 @@
       { layer: "Pselect", tag: "PS", color: colorbrewer.Reds[3][1] },
       { layer: "Nselect", tag: "NS", color: colorbrewer.Reds[3][1] },
       { layer: "Fin", tag: "Fin", color: "green" },
-      { layer: "Diffcon", tag: "DC", color: "magenta" },
+      { layer: "Diffcon", tag: "DC", color: "grey" },
       { layer: "Polycon", tag: "PC", color: "magenta" },
       { layer: "Poly", tag: "PL", color: "cyan" },
       { layer: "viad", tag: "vd", color: "black" },

align/cmdline.py

@@ -52,7 +52,7 @@ def __init__(self, *args, **kwargs):
         parser.add_argument("-n",
                             "--nvariants",
                             type=int,
-                            default=1,
+                            default=4,
                             help='Number of layout candidates to (attempt to) generate')
         parser.add_argument("-e",
                             "--effort",
@@ -102,7 +102,7 @@ def __init__(self, *args, **kwargs):
 
         parser.add_argument('--router_mode',
                             type=str,
-                            default='top_down',
+                            default='bottom_up',
                             choices=['top_down','bottom_up','collect_pins','no_op'],
                             help='Router mode')
 
@@ -111,7 +111,7 @@ def __init__(self, *args, **kwargs):
                             help='Run in GUI mode')
 
         parser.add_argument('--skipGDS',
-                            action='store_true',
+                            action='store_false',
                             help='Don\'t generate GDS files.')
 
         parser.add_argument('--lambda_coeff',

align/compiler/compiler.py

@@ -33,7 +33,7 @@ def generate_hierarchy(
     )
     annotate_library(ckt_data, primitive_library)
     primitives = PrimitiveLibrary(ckt_data, pdk_dir).gen_primitive_collateral()
-    constraint_generator(ckt_data)
+    # constraint_generator(ckt_data) # Intentionally turned off due to suboptimalities
     compiler_output(ckt_data, design_name, output_dir, primitives)
 
     return primitives

align/compiler/find_constraint.py

@@ -472,8 +472,8 @@ def filter_symnet_const(self, pairs: list):
                                 pins1=s1,
                                 pins2=s2
                             )
-                            self.iconst.append(symmnet)
-                        logger.debug(f"adding symmetric net const: {symmnet}")
+                        #     self.iconst.append(symmnet)
+                        # logger.debug(f"adding symmetric net const: {symmnet}")
                     else:
                         logger.debug(f"Skip symmetry: large fanout nets {key} {value} {pairs}")
                         # TODO Need update in placer to simplify this

align/main.py

@@ -108,7 +108,6 @@ def start_viewer(working_dir, pnr_dir, variant):
 
     stderr = sys.stderr
     Handler = functools.partial(http.server.SimpleHTTPRequestHandler, directory=str(working_dir/'Viewer'))
-
     host_name = socket.getfqdn()
     with socketserver.TCPServer((host_name, 0), Handler) as httpd:
         logger.info(f'Please view layout at http://{host_name}:{httpd.server_address[1]}/?design={variant}')

align/pnr/build_pnr_model.py

@@ -135,7 +135,8 @@ def _attach_constraint_files( DB, fpath):
         if fp.exists():
             with fp.open("rt") as fp:
                 jsonStr = fp.read()
-            logger.info(f"Reading contraint json file {curr_node.name}.pnr.const.json")
+            logger.info(f"Reading contraint json file {curr_node.name}.pnr.const.json\n")
+
             DB.ReadConstraint_Json(curr_node, jsonStr)
             logger.debug(f"Finished reading contraint json file {curr_node.name}.pnr.const.json")
         else:

align/pnr/write_constraint.py

@@ -67,7 +67,8 @@ def map_valid_const(self, all_const, module):
                 del const['instances']
 
             # Exclude constraints not to be exposed to PnR
-            if const['const_name'] in ['DoNotIdentify', 'GroupBlocks', 'DoNotUseLib', 'ConfigureCompiler', 'SameTemplate', 'PlaceOnBoundary']:
+            skip_constraints = {'DoNotIdentify', 'GroupBlocks', 'DoNotUseLib', 'ConfigureCompiler', 'SameTemplate', 'SymmetricNets', 'PlaceOnBoundary'}
+            if const['const_name'] in skip_constraints:
                 continue
 
             # Exclude constraints that need to be to multiple constraints

align/schema/constraint.py

@@ -885,13 +885,13 @@ class ConfigureCompiler(SoftConstraint):
         }
     '''
     is_digital: bool = False  # Annotation and auto-constraint generation
-    auto_constraint: bool = True  # Auto-constraint generation
-    identify_array: bool = True  # Forbids/Allow any array identification
-    fix_source_drain: bool = True  # Auto correction of source/drain terminals of transistors.
+    auto_constraint: bool = False  # Auto-constraint generation
+    identify_array: bool = False  # Forbids/Allow any array identification
+    fix_source_drain: bool = False  # Auto correction of source/drain terminals of transistors.
     remove_dummy_hierarchies: bool = True  # Removes any single instance hierarchies.
-    remove_dummy_devices: bool = True  # Removes dummy transistors
-    merge_series_devices: bool = True  # Merge series/stacked MOS/RES/CAP
-    merge_parallel_devices: bool = True  # Merge parallel devices
+    remove_dummy_devices: bool = False  # Removes dummy transistors
+    merge_series_devices: bool = False  # Merge series/stacked MOS/RES/CAP
+    merge_parallel_devices: bool = False  # Merge parallel devices
     same_template: bool = True  # generates identical layouts for all existing hierarchies in the input netlist
     propagate: bool = True  # propagate constraint to all lower hierarchies