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docs: track sub-64 multi-batch runs in results matrix; mark old lineage stale#80

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booth-algo merged 2 commits into
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docs/results-matrix-sub64
Jun 2, 2026
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docs: track sub-64 multi-batch runs in results matrix; mark old lineage stale#80
booth-algo merged 2 commits into
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docs/results-matrix-sub64

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Summary

Refreshes the emulator results matrix for the native non-packed batch_size>1 decoder work
(including true sub-64), and flags the pre-existing rows as stale.

Added — 2026-06-01 native SmolVLM2-256M-text decoder (1L, seq=4)

MLEN/BLEN batch ISA Wall (emu) Allclose MAE
64/16 2 148K 34s 97.37% 0.052
16/4 2 1.24M 17s 99.07% 0.037
32/4 2 1.16M 3.37h 99.67% 0.034
64/16 1 73K 99.96% 0.031

True sub-64 (head_dim 64 > mlen) multi-batch previously raised NotImplementedError.

Notable finding

32/32/4 took ~720× longer than 16/16/4 (3.37h vs 17s) despite fewer ISA lines — host wall
time is not ISA-proportional for cycle-accurate sub-64 emulation at mlen=32. Worth flagging for
anyone budgeting sub-64 emulator time.

Stale-lineage note

All rows ≤ 2026-05-26 are pinned to the superseded exp/roll-attention-head-batch lineage
(45c02b8); main has advanced well past it, so their Repro @HEAD? is unverified. Marked
stale rather than re-run (40+ rows, several multi-hour on the shared box).

Companion code PRs: PLENA_Compiler #55 · PLENA_Tools #6 · PLENA_Simulator #79.

…ld lineage stale

Adds four 2026-06-01 native SmolVLM2-256M-text decoder rows (batch=2 @64/64/16,
16/16/4, 32/32/4 and the batch=1 baseline) with ISA/wall/allclose/MAE, surfacing
that 32/32/4 sub-64 emulation is ~720x slower than 16/16/4 (3.37h vs 17s) despite
fewer ISA lines -- host wall time is not ISA-proportional at sub-64 mlen=32.

Adds a lineage note flagging that all rows <= 2026-05-26 are on the superseded
exp/roll-attention-head-batch lineage (45c02b8) and their Repro@HEAD is unverified
against current main (marked stale rather than re-run).
… rows

The earlier version recorded only host wall time, which is box-load-dependent and not
an accelerator metric. The 32/32/4 "3.37h / 720x slower / pathologically slow" note was
wrong: that was box contention. An identical quiet-box re-run took 106s and the simulated
latency is a normal 16.42ms (in line with 16/16/4's 10.03ms).

Recover and record simulated latency (executor.now()) for all four 2026-06-01 rows
(64/64/16 b2 = 2.39ms, 16/16/4 b2 = 10.03ms, 32/32/4 b2 = 16.42ms, 64/64/16 b1 = 1.28ms);
rename the column to Sim lat and document that earlier rows hold host wall time and are
stale. The harness now captures sim_latency_ns automatically.
@booth-algo booth-algo merged commit 8fa319c into main Jun 2, 2026
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@booth-algo booth-algo deleted the docs/results-matrix-sub64 branch June 2, 2026 00:43
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