YARPOSE.PyMTI/sample2.py at main · yarpose/YARPOSE.PyMTI · GitHub

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from PyMTI import *
import subprocess

vcd_name = "ring4bd2.vcd"
save_name = "ring4bd2.svg"
do_name = "helloworld.do"
save_title = "Sample Timing Model"

do_file_content = """
##################################
# A very simple modelsim do file #
##################################

# 1) Create a library for working in
vlib work

# 2) Compile the half adder
#vcom -93 -explicit -work work HalfAdder.vhd

# 2) Compile the half adder
vlog  ring4bd.v
vlog  ring4bd_test.v

# 3) Load it for simulation
vsim ring4bd_test

# 4) Open some selected windows for viewing
view structure
view signals
view wave

# 5) Show some of the signals in the wave window
add wave -noupdate -divider -height 32 Inputs
add wave -noupdate mode
add wave -noupdate clock
add wave -noupdate reset
add wave -noupdate -divider -height 32 Outputs
add wave -noupdate count

# 6) Set some test patterns

# a = 0, b = 0 at 0 ns
#force a 0 0
#force b 0 0

# a = 1, b = 0 at 10 ns
#force a 1 10

# a = 0, b = 1 at 20 ns
#force a 0 20
#force b 1 20

# a = 1, b = 1 at 30 ns
#force a 1 30

# 7) Run the simulation for 40 ns
run 3600
quit -f
"""

with open(do_name, "w") as file:
    file.write(do_file_content)

if __name__ == "__main__":
    # List your Verilog source files here
    verilog_files = ["ring4bd.v", "ring4bd_test.v"]
    # Parse modules and ports
    modules = parse_verilog_files(verilog_files)
    # Detect module instances to build hierarchy
    modules = find_module_instances(verilog_files, modules)
    # Print design summary
    print_summary(modules)
    # Find top modules (not instantiated by others)
    top_modules = find_top_modules(modules)
    if not top_modules:
        print("[ERROR] No top module detected!")
        exit(1)
    print(f"Top module(s) detected: {top_modules}")
    # Use first top module for simulation
    top_module = top_modules[0]
    # Generate ModelSim DO file
    generate_do_file(modules, verilog_files, top_module, do_filename="helloworld2.do", sim_time=3600)
    # Run the vsim command with arguments as a list
    subprocess.run(["vsim", "-c", "-do", "helloworld2.do"])
    signals = (
               ("ring4bd_test.mode", "mode"),
               ("ring4bd_test.clock", "Clock"),
               ("ring4bd_test.reset", "Reset"),
               ("ring4bd_test.count[3]", "count[3]"),
               ("ring4bd_test.count[2]", "count[2]"),
               ("ring4bd_test.count[1]", "count[1]"),
               ("ring4bd_test.count[0]", "count[0]"),
              )
    analog_signal = ("ring4bd_test.dut.clock","Analog Signal")
    plot(vcd_name, save_name, save_title, signals, analog_signal)