Chaper 9

Author: garciaj503

AR/09_automation_part_2/09_automation_part_2.tex

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+% Source: CPTR 280 Computer Organization and Assembly Language Fall 2023
+% File: "09 Automation (part 2) (key).pdf"
+% Author: James Foster, pogil@jgfoster.net
+
+% comment out for student version
+% \ifdefined\Student\relax\else\def\Teacher{}\fi
+
+\documentclass[12pt]{article}
+
+\title{Activity 9: Addressable Memory}
+\author{James Foster}
+\newcommand{\activityeditor}{James Foster}
+\newcommand{\activitysource}{\url{pogil@jgfoster.net}}
+\date{Fall 2023}
+
+\input{../../cspogil.sty}
+\usepackage{graphicx}
+\usepackage{tabularx}
+
+\begin{document}
+
+  \begin{center}
+    \maketitle
+    \rolenames
+  \end{center}
+
+  \keyquestions{
+  \item Model 1, Question \#5
+  \item Model 2, Question \#11
+  \item Model 3, Question \#20
+  }
+
+  \newpage
+  \maketitle
+
+  We have looked a simple programmable computer. Now we add hardware and instructions for storing the code and the data in the same memory module.
+  
+  \guides{
+    \item Do 16-bit math with 8-bit memory.
+   }{
+    \item No additional process skills.
+   }{
+    No additional notes
+   }
+
+  \input{load_instruction.tex}
+  \newpage
+  \input{addressable_memory.tex}
+  \newpage
+  \input{multi_byte_numbers.tex}
+
+\end{document}

AR/09_automation_part_2/addressable_memory.tex

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+  \model{Addressable Memory}
+
+  \vspace{10pt}
+  \begin{center}
+    \includegraphics[width=0.85\textwidth]{figures/addressable_memory.png}
+    \par\vspace{5pt}
+    {\small Figure 3: Addressable Memory}
+  \end{center}
+
+  Figure 3 shows the final major enhancement to the computer we are building.
+  \begin{itemize}
+    \item To the 16-Bit Program Counter (PC) we have added a Set control line that allows us to set the next instruction address to a 16-bit value obtained from the bottom two 8-bit (address) latches.
+    \item The memory address for read/write is now specified by either the PC or the bottom two (address) latches based on a Select control line sent to the 2-1 Address Selector.
+    \item Instead of having separate memory for code and data, we now share the memory (reducing cost and increasing flexibility).
+    \item Instead of having a sequence of 8-bit instruction codes, we now have instructions made of an 8-bit opcode (operation code) followed by a 16-bit address (operand location). These values are read into the three latches shown in three consecutive clock ticks.
+    \item Not shown are the instruction Decoder (to the right of the arrow labeled ``Code''), the 8-Bit Adder and the 8-Bit Data Latch (to the right of the arrows labeled ``8-Bit Data''), and the control lines coming out from the Decoder (the endpoints are shown with the affected components).
+  \end{itemize}
+
+  \newpage
+
+  {\it\large Refer to Model 2 above as your team develops consensus answers
+  to the questions below.}
+
+  \quest{15 min}
+
+  \Q What was the previous instruction size? What is the new instruction size? By what factor has the overall size of the instructions increased?
+    \begin{answer}[0.5in]
+      Previous instruction size: 1; new instruction size: 3; instruction size grew by 3x.
+    \end{answer}
+
+  \Q Assuming that we can still read only one byte per clock cycle and that the clock speed is the same, what is the impact on speed by the instruction size changes?
+    \begin{answer}[0.5in]
+      One-third the speed.
+    \end{answer}
+
+  \Q In Figure 1, what happened to the counter on each clock tick?
+    \begin{answer}[0.5in]
+      Counter increases by one.
+    \end{answer}
+
+  \Q In Figure 1, what can be done to change the value of the counter to something other than the next integer? What value(s) (if any) can be assigned to the program counter?
+    \begin{answer}[0.5in]
+      Clear will reset it to zero.
+    \end{answer}
+
+  \Q What new control line is added to the program counter in Figure 3? What does it do?
+    \begin{answer}[0.5in]
+      Set0 will take the values from high and low latches and put it into the counter.
+    \end{answer}
+
+  \Q What is the impact of allowing a ``Set'' instruction (``Jump'') for the Program\key\\[-2.5mm] Counter?
+    \begin{answer}[0.5in]
+      We can now specify an address for the next instruction, so loop or skip.
+    \end{answer}
+
+  \Q In Figure 1, what determines which address in memory will be provided to the adder?
+    \begin{answer}[0.5in]
+      The counter.
+    \end{answer}
+
+  \Q What new component is added in Figure 3 between the counter and the memory?
+    \begin{answer}[0.5in]
+      The 2-to-1 Address Selector and a Select control line.
+    \end{answer}
+
+  \Q In Figure 3, what determines which address in memory will be provided as output?
+    \begin{answer}[0.5in]
+      The 2-to-1 Address Selector selects either the Counter or the High and Low Latches.
+    \end{answer}
+
+  \Q What is the impact of allowing a load/add/store instruction to specify an address?
+    \begin{answer}[0.5in]
+      We can now select something other than the counter, so the data can be in a separate location from the code.
+    \end{answer}
+
+  \Q A variation of the Jump command is a Conditional Jump where the change to the PC happens only on if some specified condition exists. What conditions would be interesting?
+    \begin{answer}[0.5in]
+      Zero, non-zero, carry on or off, value negative or positive.
+    \end{answer}

AR/09_automation_part_2/figures/8bit_adder.png

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+\model{Load Instruction}
+
+  \vspace{10pt}
+  \begin{center}
+    \includegraphics[width=0.7\textwidth]{figures/programmable_computer_part2.png}
+    \par\vspace{5pt}
+    {\small Figure 1: Programmable Computer}
+  \end{center}
+
+  \vspace{10pt}
+  \begin{center}
+    \begin{tabular}{|l|c|c|}
+      \hline
+      \textbf{Instruction} & \textbf{Hexadecimal Code} & \textbf{Binary Code} \\
+      \hline
+      Add (data to latch) & 0x00 & 0000 0000 \\
+      \hline
+      Clear (latch) & 0x01 & 0000 0001 \\
+      \hline
+      Subtract (data from latch) & 0x02 & 0000 0010 \\
+      \hline
+      Stop (the clock) & 0x04 & 0000 0100 \\
+      \hline
+      Store (latch to data) & 0x08 & 0000 1000 \\
+      \hline
+    \end{tabular}
+  \end{center}
+
+  Figure 1 (copied from the previous lesson) shows a simple programmable computer with the following characteristics:
+  \begin{itemize}
+    \item A counter with 16-bit output that will increment on each clock tick (it can be reset to zero with the Start control line),
+    \item Separate addressable memory for code and data that each output an 8-bit value based on the same 16-bit address (the value of the data memory can be set to the current data latch value by the Store control line),
+    \item An 8-bit adder that calculates the sum (or difference based on the Subtract control line) of the latch and the value from memory,
+    \item A latch that captures the result of the adder on each clock tick (or is cleared based on the Clear sum control line), and
+    \item A decoder that takes each 8-bit instruction and sets the control lines appropriately.
+  \end{itemize}
+
+  \newpage
+
+  {\it\large Refer to Model 1 above as your team develops consensus answers
+  to the questions below.}
+
+  \quest{15 min}
+
+  \Q In Figure 1, the data path into the latch comes from what component?
+    \hfill\ans[1in]{Adder}
+
+  \Q In Figure 1, what two instructions are required to get the value of a single memory location into the latch?
+    (Hint: what would you add to a value to get the same value?)
+    \begin{answer}[0.5in]
+      Clear, Add
+    \end{answer}
+
+  Figure 2 adds a new control line and a new component to our computer.
+
+  \vspace{10pt}
+  \begin{center}
+    \includegraphics[width=0.5\textwidth]{figures/load_instruction.png}
+    \par\vspace{5pt}
+    {\small Figure 2: Load Instruction}
+  \end{center}
+
+  \Q What are the new elements?
+    \hfill\ans{A 2-to-1 Selector and a Selection control line}
+
+  \vspace{10pt}
+  A 2-to-1 Selector will pass on one of two inputs based on a control line. In this configuration, if the control line is 0,
+  then the value from the adder will be passed to the latch. If the control line is 1, then the value from memory will be passed to the latch.
+
+  \Q How does this circuit simplify loading a value from memory into the latch?
+    \begin{answer}[0.5in]
+      Now it takes only one instruction.
+    \end{answer}
+
+  \Q Suggest a name and a code for this instruction. (Hint: see the name of Figure 2\key\\[-2.5mm] and the pattern of hexadecimal codes used for previous instructions.)
+    \begin{answer}[0.5in]
+      Load (0x10)
+    \end{answer}

AR/09_automation_part_2/figures/add_with_carry.png

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+\model{Multi-Byte Numbers}
+
+  {\it\large Refer to Model 3 above as your team develops consensus answers
+  to the questions below.}
+
+  \quest{20 min}
+
+  \Q Consider the expression with two unsigned integers: (1100 0001$_2$ + 0100 0011$_2$).
+    \begin{itemize}
+      \item What is the binary sum?
+        \hfill\ans{1 0000 0100}
+      \item How many bits are required for the answer?
+        \hfill\ans{9}
+    \end{itemize}
+
+  \Q Consider the 8-Bit Adder shown in Figure 4.
+    \vspace{10pt}
+    \begin{center}
+      \includegraphics[width=0.3\textwidth]{figures/8bit_adder.png}
+      \par\vspace{5pt}
+      {\small Figure 4: 8-Bit Adder}
+    \end{center}
+    \begin{itemize}
+      \item What are the data path widths (number of bits) for A, B, and Sum?
+        \hfill\ans[1.5in]{8, 8, and 8}
+
+      \item What are the data path widths for Carry In and Carry Out?
+        \hfill\ans[1in]{1 and 1}
+
+      \item How is this 8-Bit Adder different from the one shown in Figure 1?
+        \begin{answer}[0.75in]
+          It has a carry in and carry out.
+        \end{answer}
+
+      \item If you were to use this 8-Bit Adder in the circuit shown in Figure 1, what value would you need for Carry In?
+        What circuit component (from an earlier lesson) would you attach to the Carry In line to do proper math?
+        \begin{answer}[1in]
+          Carry in should always be zero; this can be achieved with ground.
+        \end{answer}
+
+      \item What component would you add to the Carry Out line to ignore the overflow bit?
+        \begin{answer}[0.75in]
+          Carry out could be attached to ground.
+        \end{answer}
+
+      \item If the carry lines are ignored for simple 8-bit addition, why do they exist?
+        \begin{answer}[0.75in]
+          So that we can do complex addition (say, 16-bit values).
+        \end{answer}
+    \end{itemize}
+  
+  \vspace{-40pt}
+
+  \Q Consider the expression with two unsigned hexadecimal integers: (2345$_{16}$ + 3456$_{16}$)\key\\[-2.5mm]
+    \begin{itemize}
+      \item How many bits are required for each number?
+        \begin{answer}[0.5in]
+          4 bits for each digit, so 16-bits for each number.
+        \end{answer}
+
+      \item How many bits are required to represent the sum?
+        \begin{answer}[0.5in]
+          The value 579B$_{16}$ is also just 16 bits.
+        \end{answer}
+
+      \item Describe how you would use an 8-Bit Adder to perform this operation.
+        \begin{answer}[1.5in]
+          Add the low-order bytes: 45$_{16}$ + 56$_{16}$ = 9B$_{16}$ \\
+          Add the high-order bytes: 23$_{16}$ + 34$_{16}$ = 57$_{16}$ \\
+          Combine the high-order and low-order bytes to get the result of 579B$_{16}$
+        \end{answer}
+    \end{itemize}
+
+  \Q Consider the expression with two unsigned hexadecimal integers: (2385$_{16}$ + 3496$_{16}$).
+    \begin{itemize}
+      \item How would you use the Carry In line to add the low-order 8 bits (85$_{16}$ + 96$_{16}$)?
+        \begin{answer}[0.75in]
+          The carry-in value should be zero.
+        \end{answer}
+
+      \item How would you use the Carry In line to add the high-order 8 bits?
+        \begin{answer}[1in]
+          The carry-in value for the high-order addition should be the (saved) carry out for the low-order addition.
+        \end{answer}
+
+      \item Suggest a name for this new kind of Add command.
+        \begin{answer}[0.75in]
+          Add with carry.
+        \end{answer}
+    \end{itemize}
+
+  \Q What does the circuit in Figure 1 use to hold intermediate 8-bit sums?
+    \begin{answer}[0.75in]
+      An 8-bit latch.
+    \end{answer}
+
+  \Q What has been added in Figure 5 compared to Figure 4?
+    \vspace{10pt}
+    \begin{center}
+      \includegraphics[width=0.35\textwidth]{figures/add_with_carry.png}
+      \par\vspace{5pt}
+      {\small Figure 5: Add with Carry}
+    \end{center}
+
+    \begin{answer}[0.75in]
+      A Use Carry control line and a carry buffer or latch.
+    \end{answer}
+
+  \Q If we used 0x20 as the code for the Add with Carry instruction, how would it differ from the Add instruction code?
+    \begin{answer}[1in]
+      It has a 1 in bit 5 (the 6th bit from the right), while all other are 0.
+    \end{answer}
+
+  \Q If we attached bit 5 of the instruction decoder to the ``Use Carry'' control line, what logic gate(s) would provide the desired behavior?
+    \begin{answer}[1in]
+      An AND gate would have a 1 out if both the carry latch and the use carry control line are 1.
+    \end{answer}