Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into pres_fac_max

Author: amin1377

.github/scripts/install_dependencies.sh

@@ -29,6 +29,7 @@ sudo apt install -y \
   libncurses5-dev \
   libx11-dev \
   libxft-dev \
+  libxml2-utils \
   libxml++2.6-dev \
   libreadline-dev \
   tcllib \

CMakeLists.txt

@@ -418,11 +418,13 @@ if(${WITH_PARMYS}) # define cmake params to compile Yosys
         set(MAKE_PROGRAM "make")
     endif()
 
-    if(NOT DEFINED "${CMAKE_BUILD_PARALLEL_LEVEL}")
-        set(CUSTOM_BUILD_PARALLEL_LEVEL 16)
-    else()
-        set(CUSTOM_BUILD_PARALLEL_LEVEL "${CMAKE_BUILD_PARALLEL_LEVEL}")
-    endif()
+    # Commented out since a make file should not call another make command with
+    # threads. It should pass this information from the parent automatically.
+    # if(NOT DEFINED "${CMAKE_BUILD_PARALLEL_LEVEL}")
+    #     set(CUSTOM_BUILD_PARALLEL_LEVEL 16)
+    # else()
+    #     set(CUSTOM_BUILD_PARALLEL_LEVEL "${CMAKE_BUILD_PARALLEL_LEVEL}")
+    # endif()
     add_subdirectory(yosys)
 endif()
 

Dockerfile

@@ -1,4 +1,4 @@
-FROM ubuntu:20.04
+FROM ubuntu:22.04
 ARG DEBIAN_FRONTEND=noninteractive
 # set out workspace
 ENV WORKSPACE=/workspace
@@ -19,6 +19,7 @@ RUN apt-get update -qq \
     libtbb-dev \
     python3-pip \
     git \
+    time \
 # Install python packages
     && pip install -r requirements.txt \
 # Cleanup

blifexplorer/CMakeLists.txt

@@ -2,7 +2,7 @@ cmake_minimum_required(VERSION 3.16)
 
 project("blifexplorer")
 
-set(CMAKE_CXX_STANDARD 14)
+set(CMAKE_CXX_STANDARD 17)
 set(CMAKE_CXX_STANDARD_REQUIRED ON)
 set(CMAKE_CXX_EXTENSIONS OFF)
 

blifexplorer/src/container.cpp

@@ -929,25 +929,23 @@ void Container::showActivity()
 
 void Container::getActivityInformation()
 {
-    //right now it is a dummy function. the activity values are
-    //generated randomly
+    // Right now, it is a dummy function. The activity values are
+    // generated randomly.
     QHash<QString, nnode_t *>::const_iterator blockIterator = odinTable.constBegin();
 
     while(blockIterator != odinTable.constEnd()){
-         QString name = blockIterator.key();
-         LogicUnit* visNode = unithashtable[name];
-         //get all connections outgoing and advise them to
-         //represent the activity by color
-         QList<Wire*> outgoingWires = visNode->getOutCons();
-         foreach(Wire* wire, outgoingWires){
-             int act = qrand() % 255;
-             wire->setActivity(act);
-
-         }
+        QString name = blockIterator.key();
+        LogicUnit* visNode = unithashtable[name];
+        // Get all connections outgoing and advise them to
+        // represent the activity by color.
+        QList<Wire*> outgoingWires = visNode->getOutCons();
+        foreach(Wire* wire, outgoingWires){
+            int act = QRandomGenerator::global()->bounded(255); // Use QRandomGenerator
+            wire->setActivity(act);
+        }
         ++blockIterator;
     }
 }
-
 /*---------------------------------------------------------------------------------------------
  * (function: showSimulationStep)
  *-------------------------------------------------------------------------------------------*/

blifexplorer/src/mainwindow.cpp

@@ -271,10 +271,10 @@ void MainWindow::fontSizeChanged(const QString &)
  *-------------------------------------------------------------------------------------------*/
 void MainWindow::sceneScaleChanged(int scale)
 {
-    double newScale = scale/100.0;
-    QMatrix oldMatrix = view->matrix();
-    view->resetMatrix();
-    view->translate(oldMatrix.dx(), oldMatrix.dy());
+    double newScale = scale / 100.0;
+    QTransform oldTransform = view->transform(); // Use transform() instead of matrix()
+    view->resetTransform(); // Changed from resetMatrix() to resetTransform()
+    view->translate(oldTransform.dx(), oldTransform.dy()); // Use dx() and dy() from QTransform
     view->scale(newScale, newScale);
 }
 
@@ -915,7 +915,7 @@ void MainWindow::openFileWithOdin(){
                                                    tr("Open BLIF"),
                                                    QDir::homePath(),
                                                    tr("BLIF files (*.blif);;All files (*.*)"),
-                                                   0,
+                                                nullptr, // No parent,
                                                    QFileDialog::DontUseNativeDialog);
 
     myContainer->setFilename(actBlifFilename);
@@ -925,10 +925,10 @@ void MainWindow::openFileWithOdin(){
         //An error occured
         QMessageBox msgBox(QMessageBox::Warning, tr("No Structure Found in File"),
                            "The file you tried to explore does not contain any structures or could not be opened. Please select another file."
-                           , 0, this);
-        msgBox.addButton(tr("Open &Again"), QMessageBox::AcceptRole);
-        msgBox.addButton(tr("&Continue"), QMessageBox::RejectRole);
-        if (msgBox.exec() == QMessageBox::AcceptRole)
+                           
+                           , QMessageBox::Open | QMessageBox::Cancel, this);
+        msgBox.setDefaultButton(QMessageBox::Open);
+        if (msgBox.exec() == QMessageBox::Open)
             openFileWithOdin();
 
     }else{

dev/DOCKER_DEPLOY.md

@@ -1,52 +1,62 @@
-Overview
-========
+# Building VTR on Docker
 
+## Overview
 Docker creates an isolated container on your system so you know that VTR will run without further configurations nor affecting any other work.
 
 Our Docker file sets up this enviroment by installing all necessary Linux packages and applications as well as Perl modules.
 
-Additionally, Cloud9 is installed, which enables the remote management of your container through browser. With Cloud9, VTR can be started easier (and even modified and recompiled) without the need to logging into a terminal. If the Cloud9 endpoint is published outside your LAN, you can also execute VTR remotely or share your screen with other users.
+## Setup
 
+1. Install docker (Community Edition is free and sufficient for VTR): https://docs.docker.com/engine/install/
 
-Setup
-=====
+2. Clone the VTR project:
 
-Install docker (Community Edition is free and sufficient for VTR): https://docs.docker.com/engine/installation/
+    ```
+    git clone https://github.com/verilog-to-routing/vtr-verilog-to-routing
+    ```
 
-Clone the VTR project:
+3. CD to the VTR folder and build the docker image:
 
-`git clone https://github.com/verilog-to-routing/vtr-verilog-to-routing`
+    ```
+    docker build . -t vtrimg
+    ```
 
-CD to the VTR folder and build the docker image:
+4. Start docker with the new image:
 
-`docker build . -t vtrimg`
+    ```
+    docker run -it -d --name vtr vtrimg
+    ```
 
-Start docker with the new image and connect the current volume with the workspace volume of the container:
 
-`sudo docker run -it -d -p <port-to-open-on-host>:8080 -v <absolute-path-to-VTR-folder>:/workspace vtrimg`
+## Running
 
+1. Attach to the Docker container. Attaching will open a shell on the `/workspace` directory within the container.
+The project root directory from the docker build process is copied and placed in the `/workspace` directory.
 
-Running
-=======
+    ```sh
+    # from host computer
+    docker exec -it vtr /bin/bash
+    ```
 
-Open a browser (Google Chrome for example) and navigate to your host's url at the port you opened up. For example:
-http://192.168.1.30:8080
+1. Verfiy that VTR has been installed correctly:
 
-First, use one of the terminals and compile VTR:
-make && make installation/
+    ```sh
+    # in container
+    ./vtr_flow/scripts/run_vtr_task.py regression_tests/vtr_reg_basic/basic_timing
+    ```
 
-Second, ensure that a basic regression test passes:
-./run_reg_test.py vtr_reg_basic
+    The expected output is:
 
-Third, run and/or modify VTR in the usual way.
+    ```
+    k6_N10_mem32K_40nm/single_ff            OK
+    k6_N10_mem32K_40nm/single_ff            OK
+    k6_N10_mem32K_40nm/single_wire          OK
+    k6_N10_mem32K_40nm/single_wire          OK
+    k6_N10_mem32K_40nm/diffeq1              OK
+    k6_N10_mem32K_40nm/diffeq1              OK
+    k6_N10_mem32K_40nm/ch_intrinsics                OK
+    k6_N10_mem32K_40nm/ch_intrinsics                OK
+    ```
 
-Developpement Debugging
-=======================
-the container already comes with clang as the default compiler and with scan-build the do statistical analysis on the build
-set to `debug` in makefile
-
-run `scan-build make -j4` from the root VTR directory.
-to output the html analysis to a specific folder, run `scan-build make -j4 -o /some/folder`
-
-the output is html and viewable in any browser.
+2. Run and/or modify VTR in the usual way.
 

doc/src/quickstart/index.rst

@@ -48,6 +48,12 @@ On most unix-like systems you can run:
 
     > make
 
+The default front-end for VTR is :ref:`Parmys<parmys>`, but you can build with ODIN II instead using the command below. This is required to run :ref:`Synthesizing with ODIN II<synthesizing_with_odin_ii>`.
+
+.. code-block:: bash
+
+    > make CMAKE_PARAMS="-DWITH_ODIN=on"
+
 from the VTR root directory (hereafter referred to as :term:`$VTR_ROOT`) to build VTR.
 
 .. note:: 
@@ -63,6 +69,8 @@ from the VTR root directory (hereafter referred to as :term:`$VTR_ROOT`) to buil
     * define VTR_ROOT as a variable in your shell (e.g. if ``~/trees/vtr`` is the path to the VTR source tree on your machine, run the equivalent of ``VTR_ROOT=~/trees/vtr`` in BASH) which will allow you to run the commands as written in this guide, or
     * manually replace `$VTR_ROOT` in the example commands below with your path to the VTR source tree.
 
+
+
 For more details on building VTR on various operating systems/platforms see :doc:`Building VTR</BUILDING>`.
 
 
@@ -235,6 +243,7 @@ Next we need to run the three main sets of tools:
 * :ref:`ABC` performs 'logic optimization' which simplifies the circuit logic, and 'technology mapping' which converts logic equations into the Look-Up-Tables (LUTs) available on an FPGA, and
 * :ref:`VPR` which performs packing, placement and routing of the circuit to implement it on the targetted FPGA architecture.
 
+.. _synthesizing_with_odin_ii:
 Synthesizing with ODIN II
 ~~~~~~~~~~~~~~~~~~~~~~~~~
 

doc/src/tutorials/flow/basic_flow.rst

@@ -17,16 +17,9 @@ The following steps show you to run the VTR design flow to map a sample circuit
 
         $VTR_ROOT/vtr_flow/scripts/run_vtr_task.py basic_no_timing 
         
-    The subdirectory ``regression_tests/vtr_reg_basic`` contains tests that are to be run before each commit. They check for basic functionallity to make sure nothing was           extremely out of order. This command runs the VTR flow on a set of circuits and a single architecture. 
+    The subdirectory ``regression_tests/vtr_reg_basic`` contains tests that are to be run before each commit. They check for basic functionality to make sure nothing was extremely out of order. This command runs the VTR flow on a set of circuits and a single architecture. 
     The files generated from the run are stored in ``basic_no_timing/run[#]`` where ``[#]`` is the number of runs you have done.
-    If this is your first time running the flow, the results will be stored in basic_no_timing/run001.
-    When the script completes, enter the following command:
-
-    .. code-block:: shell
-
-         ../../../scripts/python_libs/vtr/parse_vtr_task.py basic_no_timing/
-
-    This parses out the information of the VTR run and outputs the results in a text file called ``run[#]/parse_results.txt``.
+    If this is your first time running the flow, the results will be stored in basic_no_timing/run001. The command parses out the information of the VTR run and outputs the results in a text file called ``run[#]/parse_results.txt``.
 
     More info on how to run the flow on multiple circuits and architectures along with different options later.
     Before that, we need to ensure that the run that you have done works.

doc/src/vpr/basic_flow.rst

@@ -4,7 +4,7 @@ Basic flow
 The Place and Route process in VPR consists of several steps:
 
 - Packing (combinines primitives into complex blocks)
-- Placment (places complex blocks within the FPGA grid)
+- Placement (places complex blocks within the FPGA grid)
 - Routing (determines interconnections between blocks)
 - Analysis (analyzes the implementation)