Merge pull request #2930 from verilog-to-routing/ingest_per_edge_delay

Override edge attributes in RR graph

Author: soheilshahrouz

Makefile

@@ -48,14 +48,14 @@ ifeq ($(VERBOSE),1)
 override CMAKE_PARAMS := -DVTR_ENABLE_VERBOSE=on ${CMAKE_PARAMS}
 endif
 
-# -s : Suppresss makefile output (e.g. entering/leaving directories)
+# -s : Suppresses makefile output (e.g. entering/leaving directories)
 # --output-sync target : For parallel compilation ensure output for each target is synchronized (make version >= 4.0)
 MAKEFLAGS := -s
 
 SOURCE_DIR := $(PWD)
 BUILD_DIR ?= build
 
-#Check for the cmake exectuable
+#Check for the cmake executable
 CMAKE := $(shell command -v cmake 2> /dev/null)
 
 #Show test log on failures with 'make test'

doc/src/vpr/command_line_usage.rst

@@ -379,6 +379,14 @@ Use the options below to override this default naming behaviour.
 
     .. seealso:: :ref:`Routing Resource XML File <vpr_route_resource_file>`.
 
+.. option:: --read_rr_edge_override <file>
+
+    Reads a file that overrides the intrinsic delay of specific edges in RR graph.
+
+    This option should be used with both :option:`--read_rr_graph` and :option:`--write_rr_graph`. When used this way,
+    VPR reads the RR graph, updates the delays of selected edges using :option:`--read_rr_edge_override`,
+    and writes the updated RR graph. The modified RR graph can then be used in later VPR runs.
+
 .. option:: --read_vpr_constraints <file>
 
     Reads the :ref:`VPR constraints <vpr_constraints>` that the flow must respect from the specified XML file.

doc/src/vpr/file_formats.rst

@@ -1100,6 +1100,28 @@ To aid in handling large graphs, rr_graph files can also be :ref:`saved in <file
 
 .. _end:
 
+RR Graph Edge Attribute Override File Format (.txt)
+---------------------------------------------------
+This file lets users override attributes of specific edges in the RR graph. Currently, only the intrinsic delay (Tdel)
+can be changed. The expected format is:
+
+.. code-block:: none
+
+    # edge    Tdel
+    64812     5.9e-11
+    9981      4.2e-11
+    1234      7.1e-11
+    4321      9.4e-11
+    (42, 64)  7.3e-11
+
+.. _end:
+
+Lines starting with # are comments and ignored. Each other line should specify either: an edge ID and its new delay, or
+a source/sink node pair and its delay.
+
+This allows more accurate modeling of switch delays in the RR graph without creating many switch types
+in the architecture file and limiting them to small regions. This can be useful for more detailed modeling of
+a fabricated FPGA where layout differences lead to small delay differences in the same type of routing switch.
 
 Network-on-Chip (NoC) Traffic Flows Format (.flows)
 ---------------------------------------------------

libs/libarchfpga/src/physical_types.cpp

@@ -71,6 +71,42 @@ bool t_rr_switch_inf::configurable() const {
     return switch_type_is_configurable(type());
 }
 
+bool t_rr_switch_inf::operator==(const t_rr_switch_inf& other) const {
+    return R == other.R
+           && Cin == other.Cin
+           && Cout == other.Cout
+           && Cinternal == other.Cinternal
+           && Tdel == other.Tdel
+           && mux_trans_size == other.mux_trans_size
+           && buf_size == other.buf_size
+           && power_buffer_type == other.power_buffer_type
+           && power_buffer_size == other.power_buffer_size
+           && intra_tile == other.intra_tile
+           && type() == other.type();
+}
+
+std::size_t t_rr_switch_inf::Hasher::operator()(const t_rr_switch_inf& s) const {
+    std::size_t hash_val = 0;
+
+    auto hash_combine = [&hash_val](auto&& val) {
+        hash_val ^= std::hash<std::decay_t<decltype(val)>>{}(val) + 0x9e3779b9 + (hash_val << 6) + (hash_val >> 2);
+    };
+
+    hash_combine(s.R);
+    hash_combine(s.Cin);
+    hash_combine(s.Cout);
+    hash_combine(s.Cinternal);
+    hash_combine(s.Tdel);
+    hash_combine(s.mux_trans_size);
+    hash_combine(s.buf_size);
+    hash_combine(static_cast<int>(s.power_buffer_type));
+    hash_combine(s.power_buffer_size);
+    hash_combine(s.intra_tile);
+    hash_combine(static_cast<int>(s.type()));
+
+    return hash_val;
+}
+
 void t_rr_switch_inf::set_type(SwitchType type_val) {
     type_ = type_val;
 }

libs/libarchfpga/src/physical_types.h

@@ -1588,16 +1588,31 @@ enum class SegResType {
     NUM_RES_TYPES
 };
 
-constexpr std::array<const char*, static_cast<size_t>(SegResType::NUM_RES_TYPES)> RES_TYPE_STRING = {{"GCLK", "GENERAL"}}; //String versions of segment resource types
+/// String versions of segment resource types
+constexpr std::array<const char*, static_cast<size_t>(SegResType::NUM_RES_TYPES)> RES_TYPE_STRING{"GCLK", "GENERAL"};
 
+/// Defines the type of switch block used in FPGA routing.
 enum e_switch_block_type {
+    /// If the type is SUBSET, I use a Xilinx-like switch block where track i in one channel always
+    /// connects to track i in other channels.
     SUBSET,
+
+    /// If type is WILTON, I use a switch block where track i
+    /// does not always connect to track i in other channels.
+    /// See Steve Wilton, PhD Thesis, University of Toronto, 1996.
     WILTON,
+
+    /// The UNIVERSAL switch block is from Y. W. Chang et al, TODAES, Jan. 1996, pp. 80 - 101.
     UNIVERSAL,
+
+    /// The FULL switch block type allows for complete connectivity between tracks.
     FULL,
+
+    /// A CUSTOM switch block has also been added which allows a user to describe custom permutation functions and connection patterns.
+    /// See comment at top of SRC/route/build_switchblocks.c
     CUSTOM
 };
-typedef enum e_switch_block_type t_switch_block_type;
+
 enum e_Fc_type {
     ABSOLUTE,
     FRACTIONAL
@@ -1906,16 +1921,28 @@ struct t_rr_switch_inf {
     bool intra_tile = false;
 
   public:
-    //Returns the type of switch
+    /// Returns the type of switch
     SwitchType type() const;
 
-    //Returns true if this switch type isolates its input and output into
-    //separate DC-connected subcircuits
+    /// Returns true if this switch type isolates its input and output into
+    /// separate DC-connected subcircuits
     bool buffered() const;
 
-    //Returns true if this switch type is configurable
+    /// Returns true if this switch type is configurable
     bool configurable() const;
 
+    bool operator==(const t_rr_switch_inf& other) const;
+
+    /**
+     * @brief Functor for computing a hash value for t_rr_switch_inf.
+     *
+     * This custom hasher enables the use of t_rr_switch_inf objects as keys
+     * in unordered containers such as std::unordered_map or std::unordered_set.
+     */
+    struct Hasher {
+        std::size_t operator()(const t_rr_switch_inf& s) const;
+    };
+
   public:
     void set_type(SwitchType type_val);
 

libs/librrgraph/src/base/rr_graph_builder.h

@@ -239,7 +239,7 @@ class RRGraphBuilder {
 
     /** @brief Reserve the lists of edges to be memory efficient.
      * This function is mainly used to reserve memory space inside RRGraph,
-     * when adding a large number of edges in order to avoid memory fragements */
+     * when adding a large number of edges in order to avoid memory fragments */
     inline void reserve_edges(size_t num_edges) {
         node_storage_.reserve_edges(num_edges);
     }
@@ -264,6 +264,12 @@ class RRGraphBuilder {
         node_storage_.alloc_and_load_edges(rr_edges_to_create);
     }
 
+    /** @brief Overrides the associated switch for a given edge by
+     *         updating the edge to use the passed in switch. */
+    inline void override_edge_switch(RREdgeId edge_id, RRSwitchId switch_id) {
+        node_storage_.override_edge_switch(edge_id, switch_id);
+    }
+
     /** @brief set_node_cost_index gets the index of cost data in the list of cost_indexed_data data structure
      * It contains the routing cost for different nodes in the RRGraph
      * when used in evaluate different routing paths
@@ -304,7 +310,7 @@ class RRGraphBuilder {
     /** @brief Reserve the lists of nodes, edges, switches etc. to be memory efficient.
      * This function is mainly used to reserve memory space inside RRGraph,
      * when adding a large number of nodes/edge/switches/segments,
-     * in order to avoid memory fragements */
+     * in order to avoid memory fragments */
     inline void reserve_nodes(size_t size) {
         node_storage_.reserve(size);
     }

libs/librrgraph/src/base/rr_graph_storage.cpp

@@ -536,10 +536,9 @@ void t_rr_graph_storage::partition_edges(const vtr::vector<RRSwitchId, t_rr_swit
     //    by assign_first_edges()
     //  - Edges within a source node have the configurable edges before the
     //    non-configurable edges.
-    std::stable_sort(
-        edge_sort_iterator(this, 0),
-        edge_sort_iterator(this, edge_src_node_.size()),
-        edge_compare_src_node_and_configurable_first(rr_switches));
+    std::stable_sort(edge_sort_iterator(this, 0),
+                     edge_sort_iterator(this, edge_src_node_.size()),
+                     edge_compare_src_node_and_configurable_first(rr_switches));
 
     partitioned_ = true;
 
@@ -548,6 +547,12 @@ void t_rr_graph_storage::partition_edges(const vtr::vector<RRSwitchId, t_rr_swit
     VTR_ASSERT_SAFE(validate(rr_switches));
 }
 
+void t_rr_graph_storage::override_edge_switch(RREdgeId edge_id, RRSwitchId switch_id) {
+    VTR_ASSERT_DEBUG(partitioned_);
+    VTR_ASSERT_DEBUG(remapped_edges_);
+    edge_switch_[edge_id] = (short)((size_t)switch_id);
+}
+
 t_edge_size t_rr_graph_storage::num_configurable_edges(RRNodeId id, const vtr::vector<RRSwitchId, t_rr_switch_inf>& rr_switches) const {
     VTR_ASSERT(!node_first_edge_.empty() && remapped_edges_);
 

libs/librrgraph/src/base/rr_graph_storage.h

@@ -393,13 +393,27 @@ class t_rr_graph_storage {
      * This method should generally not be used, and instead first_edge and
      * last_edge should be used.
      */
-    RREdgeId edge_id(const RRNodeId& id, t_edge_size iedge) const {
+    RREdgeId edge_id(RRNodeId id, t_edge_size iedge) const {
         RREdgeId first_edge = this->first_edge(id);
         RREdgeId ret(size_t(first_edge) + iedge);
         VTR_ASSERT_SAFE(ret < last_edge(id));
         return ret;
     }
 
+    /**
+     * @brief Retrieve the RREdgeId that connects the given source and sink nodes.
+     *        If the given source/sink nodes are not connected, RREdgeId::INVALID() is returned.
+     */
+    RREdgeId edge_id(RRNodeId src, RRNodeId sink) const {
+        for (RREdgeId outgoing_edge_id : edge_range(src)) {
+            if (edge_sink_node(outgoing_edge_id) == sink) {
+                return outgoing_edge_id;
+            }
+        }
+
+        return RREdgeId::INVALID();
+    }
+
     /** @brief Get the source node for the specified edge. */
     RRNodeId edge_src_node(const RREdgeId& edge) const {
         VTR_ASSERT_DEBUG(edge.is_valid());
@@ -448,7 +462,7 @@ class t_rr_graph_storage {
      *
      * The following methods implement an interface that appears to be
      * equivalent to the interface exposed by std::vector<t_rr_node>.
-     * This was done for backwards compability. See t_rr_node for more details.
+     * This was done for backwards compatibility. See t_rr_node for more details.
      *
      * Proxy methods:
      *
@@ -483,8 +497,8 @@ class t_rr_graph_storage {
      ***************************/
 
     /** @brief
-     * Makes room in storage for RRNodeId in amoritized O(1) fashion.
-     * This results in an allocation pattern similiar to what would happen
+     * Makes room in storage for RRNodeId in amortized O(1) fashion.
+     * This results in an allocation pattern similar to what would happen
      * if push_back(x) / emplace_back() were used if underlying storage
      * was not pre-allocated.
      */
@@ -616,8 +630,8 @@ class t_rr_graph_storage {
     void set_node_direction(RRNodeId, Direction new_direction);
 
     /** @brief
-     * Add a side to the node abbributes
-     * This is the function to use when you just add a new side WITHOUT reseting side attributes
+     * Add a side to the node attributes
+     * This is the function to use when you just add a new side WITHOUT resetting side attributes
      */
     void add_node_side(RRNodeId, e_side new_side);
 
@@ -707,9 +721,8 @@ class t_rr_graph_storage {
      *
      * init_fan_in does not need to be invoked before this method.
      */
-     size_t count_rr_switches(
-        const std::vector<t_arch_switch_inf>& arch_switch_inf,
-        t_arch_switch_fanin& arch_switch_fanins);
+     size_t count_rr_switches(const std::vector<t_arch_switch_inf>& arch_switch_inf,
+                             t_arch_switch_fanin& arch_switch_fanins);
 
     /** @brief Maps arch_switch_inf indicies to rr_switch_inf indicies.
      *
@@ -731,6 +744,10 @@ class t_rr_graph_storage {
      */
     void partition_edges(const vtr::vector<RRSwitchId, t_rr_switch_inf>& rr_switches);
 
+    /** @brief Overrides the associated switch for a given edge by
+     *         updating the edge to use the passed in switch. */
+    void override_edge_switch(RREdgeId edge_id, RRSwitchId switch_id);
+
     /** @brief Validate that edge data is partitioned correctly.*/
     bool validate_node(RRNodeId node_id, const vtr::vector<RRSwitchId, t_rr_switch_inf>& rr_switches) const;
     bool validate(const vtr::vector<RRSwitchId, t_rr_switch_inf>& rr_switches) const;

libs/librrgraph/src/base/rr_graph_view.h

@@ -413,6 +413,11 @@ class RRGraphView {
         return node_storage_.edge_switch(id, iedge);
     }
 
+    /// @brief Returns the associated switch for a given edge.
+    inline short edge_switch(RREdgeId id) const {
+        return node_storage_.edge_switch(id);
+    }
+
     /** @brief Return the source node for the specified edge. 
     */
     inline RRNodeId edge_src_node(const RREdgeId edge_id) const {