Improving top level comments for mlp_2_phase_optimization_step_one benchmark to indicate differnce to the other MLP benchmarks

Author: Srivat97

vtr_flow/benchmarks/noc/Large_Designs/MLP/MLP_2_phase_optimization/MLP_2_phase_optimization_step_1/verilog/mlp_two_phase_optimization_step_one.v

@@ -5,6 +5,8 @@
     but limit the circuit to mostly routers. The design implements the following:
 	1) A number of NoC routers that represent MLP modules
 	2) A number of dummy logic that connect to the NoC router interfaces
+	3) The actual MVM, dispatcher and collector modules are not included in this
+	   benchmark as the goal is to minimize soft logic
 */
 
 module mlp_two_phase_optimization_step_one (