Updated golden result for strong_timing_fail

Author: jmah76

vtr_flow/sdc/samples/impossible_pass_timing.sdc

@@ -1,9 +1,3 @@
-create_clock -period 0.1 -name impossible 
+create_clock -period 0.00000001 * 
 
-set_input_delay -clock impossible 0 [get_ports{*}] 
 
-set_output_delay -clock impossible 0 [get_ports{*}]
-
-set_min_delay 0 -from [get_clocks{*}] -to [get_clocks{*}]
-
-set_max_delay 0 -from [get_clocks{*}] -to [get_clocks{*}]

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt

@@ -1,2 +1,2 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	yosys_synth_time	max_yosys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_time	placed_wirelength_est	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-k6_frac_N10_mem32K_40nm.xml	ch_intrinsics.v	common_-sdc_file_sdc/samples/impossible_pass_timing.sdc	413.40	vpr	645.85 MiB		0.76	119284	-1	-1	3	0.38	-1	-1	38156	-1	-1	65	99	1	0	exited with return code 1	v8.0.0-5549-gc7bbbb9fa	release IPO VTR_ASSERT_LEVEL=2 sanitizers	GNU 9.4.0 on Linux-5.13.0-28-generic x86_64	2022-07-01T09:16:33	betzgrp-pchenry	/home/mahjenni/Desktop/vtr-verilog-to-routing	661348	99	130	363	493	1	252	295	12	12	144	clb	auto	38.62	-1	152.24	0.89	0.792536	-24.0215	-0.792536	nan	15.23	0.0349292	0.0339611	5.66726	4.72413	40	1573	19	5.66058e+06	4.05111e+06	333335.	2314.82	92.52	15.005	13.1767	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+k6_frac_N10_mem32K_40nm.xml	ch_intrinsics.v	common_-sdc_file_sdc/samples/impossible_pass_timing.sdc	2.28	abc	37.25 MiB		0.11	9684	-1	-1	3	0.27	-1	-1	38144	-1	-1	65	99	1	0	exited with return code 1	v8.0.0-5685-geab6abbda-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-5.13.0-28-generic x86_64	2022-07-08T12:14:29	betzgrp-pchenry	/home/mahjenni/Desktop/vtr-verilog-to-routing	32460	99	130	363	493	1	251	295	12	12	144	clb	auto	0.13	-1	0.22	0.00	1.86328	-122.47	-1.86328	1.86328	0.23	0.000193134	0.000158636	0.0273733	0.0209447	40	1772	32	5.66058e+06	4.05111e+06	333335.	2314.82	0.46	0.0684697	0.0541227	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1