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[vpr][route] get ipin c from rr graph in add_rr_graph_C_from_switches
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+5
-4
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vpr/src/route/rr_graph_generation/rr_graph_timing_params.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88

99
/****************** Subroutine definitions *********************************/
1010

11-
void add_rr_graph_C_from_switches(float C_ipin_cblock) {
11+
void add_rr_graph_C_from_switches() {
1212
/* This routine finishes loading the C elements of the rr_graph. It assumes *
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* that when you call it the CHANX and CHANY nodes have had their C set to *
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* their metal capacitance, and everything else has C set to 0. The graph *
@@ -100,18 +100,19 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) {
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}
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/* End edge to CHANX or CHANY node. */
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else if (to_rr_type == e_rr_type::IPIN) {
103+
float ipin_c = rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Cin;
103104
if (INCLUDE_TRACK_BUFFERS) {
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/* Implements sharing of the track to connection box buffer.
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* Such a buffer exists at every segment of the wire at which
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* at least one logic block input connects. */
107108
icblock = seg_index_of_cblock(rr_graph, from_rr_type, to_node);
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if (cblock_counted[icblock] == false) {
109-
rr_node_C[inode] += C_ipin_cblock;
110+
rr_node_C[inode] += ipin_c;
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cblock_counted[icblock] = true;
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}
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} else {
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/* No track buffer. Simply add the capacitance onto the wire */
114-
rr_node_C[inode] += C_ipin_cblock;
115+
rr_node_C[inode] += ipin_c;
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}
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}
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} /* End loop over all edges of a node. */
Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,3 @@
11
#pragma once
22

3-
void add_rr_graph_C_from_switches(float C_ipin_cblock);
3+
void add_rr_graph_C_from_switches();

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