Skip to content

Commit afd43fa

Browse files
soheilshahrouzsoheilshahrouz
committed
rename SwitchType to e_switch_type
1 parent 3ce169c commit afd43fa

File tree

15 files changed

+79
-80
lines changed

15 files changed

+79
-80
lines changed

‎libs/libarchfpga/src/echo_arch.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -217,16 +217,16 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
217217
//It always consists of 10 alphanumeric digits, a decimal
218218
//and a sign
219219
for (int i = 0; i < (int)arch->switches.size(); i++) {
220-
if (arch->switches[i].type() == SwitchType::MUX) {
220+
if (arch->switches[i].type() == e_switch_type::MUX) {
221221
fprintf(Echo, "\tSwitch[%d]: name %s type mux\n", i + 1, arch->switches[i].name.c_str());
222-
} else if (arch->switches[i].type() == SwitchType::TRISTATE) {
222+
} else if (arch->switches[i].type() == e_switch_type::TRISTATE) {
223223
fprintf(Echo, "\tSwitch[%d]: name %s type tristate\n", i + 1, arch->switches[i].name.c_str());
224-
} else if (arch->switches[i].type() == SwitchType::SHORT) {
224+
} else if (arch->switches[i].type() == e_switch_type::SHORT) {
225225
fprintf(Echo, "\tSwitch[%d]: name %s type short\n", i + 1, arch->switches[i].name.c_str());
226-
} else if (arch->switches[i].type() == SwitchType::BUFFER) {
226+
} else if (arch->switches[i].type() == e_switch_type::BUFFER) {
227227
fprintf(Echo, "\tSwitch[%d]: name %s type buffer\n", i + 1, arch->switches[i].name.c_str());
228228
} else {
229-
VTR_ASSERT(arch->switches[i].type() == SwitchType::PASS_GATE);
229+
VTR_ASSERT(arch->switches[i].type() == e_switch_type::PASS_GATE);
230230
fprintf(Echo, "\tSwitch[%d]: name %s type pass_gate\n", i + 1, arch->switches[i].name.c_str());
231231
}
232232
fprintf(Echo, "\t\t\t\tR %e Cin %e Cout %e\n", arch->switches[i].R,

‎libs/libarchfpga/src/physical_types.cpp‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
* t_arch_switch_inf
1010
*/
1111

12-
SwitchType t_arch_switch_inf::type() const {
12+
e_switch_type t_arch_switch_inf::type() const {
1313
return type_;
1414
}
1515

@@ -44,32 +44,32 @@ void t_arch_switch_inf::set_Tdel(int fanin, float delay) {
4444
Tdel_map_[fanin] = delay;
4545
}
4646

47-
void t_arch_switch_inf::set_type(SwitchType type_val) {
47+
void t_arch_switch_inf::set_type(e_switch_type type_val) {
4848
type_ = type_val;
4949
}
5050

51-
bool switch_type_is_buffered(SwitchType type) {
51+
bool switch_type_is_buffered(e_switch_type type) {
5252
//Muxes and Tristates isolate their input and output into
5353
//separate DC connected sub-circuits
54-
return type == SwitchType::MUX
55-
|| type == SwitchType::TRISTATE
56-
|| type == SwitchType::BUFFER;
54+
return type == e_switch_type::MUX
55+
|| type == e_switch_type::TRISTATE
56+
|| type == e_switch_type::BUFFER;
5757
}
5858

59-
bool switch_type_is_configurable(SwitchType type) {
59+
bool switch_type_is_configurable(e_switch_type type) {
6060
//Shorts and buffers are non-configurable
61-
return !(type == SwitchType::SHORT
62-
|| type == SwitchType::BUFFER);
61+
return !(type == e_switch_type::SHORT
62+
|| type == e_switch_type::BUFFER);
6363
}
6464

65-
e_directionality switch_type_directionality(SwitchType type) {
66-
if (type == SwitchType::SHORT || type == SwitchType::PASS_GATE) {
65+
e_directionality switch_type_directionality(e_switch_type type) {
66+
if (type == e_switch_type::SHORT || type == e_switch_type::PASS_GATE) {
6767
//Shorts and pass gates can conduct in either direction
6868
return e_directionality::BI_DIRECTIONAL;
6969
} else {
70-
VTR_ASSERT_SAFE(type == SwitchType::MUX
71-
|| type == SwitchType::TRISTATE
72-
|| type == SwitchType::BUFFER);
70+
VTR_ASSERT_SAFE(type == e_switch_type::MUX
71+
|| type == e_switch_type::TRISTATE
72+
|| type == e_switch_type::BUFFER);
7373
//Buffered switches can only drive in one direction
7474
return e_directionality::UNI_DIRECTIONAL;
7575
}

‎libs/libarchfpga/src/physical_types.h‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -340,7 +340,7 @@ enum class PortEquivalence {
340340
* class. *
341341
* pinlist[]: List of clb pin numbers which belong to this class. */
342342
struct t_class {
343-
enum e_pin_type type;
343+
e_pin_type type;
344344
PortEquivalence equivalence;
345345
int num_pins;
346346
std::vector<int> pinlist; /* [0..num_pins - 1] */
@@ -1669,7 +1669,7 @@ struct t_segment_inf {
16691669
/// The capacitance of a routing track, per unit logic block length.
16701670
float Cmetal;
16711671

1672-
enum e_directionality directionality;
1672+
e_directionality directionality;
16731673

16741674
/**
16751675
* @brief Defines what axis the segment is parallel to. See e_parallel_axis
@@ -1753,7 +1753,7 @@ struct t_hash_segment_inf {
17531753
}
17541754
};
17551755

1756-
enum class SwitchType {
1756+
enum class e_switch_type {
17571757
MUX = 0, //A configurable (buffered) mux (single-driver)
17581758
TRISTATE, //A configurable tristate-able buffer (multi-driver)
17591759
PASS_GATE, //A configurable pass transistor switch (multi-driver)
@@ -1763,11 +1763,11 @@ enum class SwitchType {
17631763
NUM_SWITCH_TYPES
17641764
};
17651765

1766-
constexpr std::array<const char*, size_t(SwitchType::NUM_SWITCH_TYPES)> SWITCH_TYPE_STRINGS = {{"MUX", "TRISTATE", "PASS_GATE", "SHORT", "BUFFER", "INVALID"}};
1766+
constexpr std::array<const char*, size_t(e_switch_type::NUM_SWITCH_TYPES)> SWITCH_TYPE_STRINGS = {{"MUX", "TRISTATE", "PASS_GATE", "SHORT", "BUFFER", "INVALID"}};
17671767

1768-
bool switch_type_is_buffered(SwitchType type);
1769-
bool switch_type_is_configurable(SwitchType type);
1770-
e_directionality switch_type_directionality(SwitchType type);
1768+
bool switch_type_is_buffered(e_switch_type type);
1769+
bool switch_type_is_configurable(e_switch_type type);
1770+
e_directionality switch_type_directionality(e_switch_type type);
17711771

17721772
/* Constant/Reserved names for switches in architecture XML
17731773
* Delayless switch:
@@ -1836,7 +1836,7 @@ struct t_arch_switch_inf {
18361836

18371837
public:
18381838
//Returns the type of switch
1839-
SwitchType type() const;
1839+
e_switch_type type() const;
18401840

18411841
//Returns true if this switch type isolates its input and output into
18421842
//separate DC-connected subcircuits
@@ -1856,10 +1856,10 @@ struct t_arch_switch_inf {
18561856

18571857
public:
18581858
void set_Tdel(int fanin, float delay);
1859-
void set_type(SwitchType type_val);
1859+
void set_type(e_switch_type type_val);
18601860

18611861
private:
1862-
SwitchType type_ = SwitchType::INVALID;
1862+
e_switch_type type_ = e_switch_type::INVALID;
18631863

18641864
/**
18651865
* @brief Maps the number of inputs to a delay.

‎libs/libarchfpga/src/read_fpga_interchange_arch.cpp‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2368,15 +2368,15 @@ struct ArchReader {
23682368
t_arch_switch_inf* as = &arch_->switches[i];
23692369

23702370
R = Cin = Cint = Cout = Tdel = 0.0;
2371-
SwitchType type;
2371+
e_switch_type type;
23722372

23732373
if (i == 0) {
23742374
switch_name = "short";
2375-
type = SwitchType::SHORT;
2375+
type = e_switch_type::SHORT;
23762376
R = 0.0;
23772377
} else if (i == 1) {
23782378
switch_name = "generic";
2379-
type = SwitchType::MUX;
2379+
type = e_switch_type::MUX;
23802380
R = 0.0;
23812381
} else {
23822382
auto entry = pip_timing_models_list[i - 2];
@@ -2404,7 +2404,7 @@ struct ArchReader {
24042404
name << "Tdel" << std::scientific << Tdel;
24052405

24062406
switch_name = name.str() + std::to_string(i);
2407-
type = entry.first ? SwitchType::MUX : SwitchType::PASS_GATE;
2407+
type = entry.first ? e_switch_type::MUX : e_switch_type::PASS_GATE;
24082408
}
24092409

24102410
/* Should never happen */
@@ -2415,15 +2415,15 @@ struct ArchReader {
24152415

24162416
as->name = switch_name;
24172417
as->set_type(type);
2418-
as->mux_trans_size = as->type() == SwitchType::MUX ? 1 : 0;
2418+
as->mux_trans_size = as->type() == e_switch_type::MUX ? 1 : 0;
24192419

24202420
as->R = R;
24212421
as->Cin = Cin;
24222422
as->Cout = Cout;
24232423
as->Cinternal = Cint;
24242424
as->set_Tdel(t_arch_switch_inf::UNDEFINED_FANIN, Tdel);
24252425

2426-
if (as->type() == SwitchType::SHORT || as->type() == SwitchType::PASS_GATE) {
2426+
if (as->type() == e_switch_type::SHORT || as->type() == e_switch_type::PASS_GATE) {
24272427
as->buf_size_type = BufferSize::ABSOLUTE;
24282428
as->buf_size = 0;
24292429
as->power_buffer_type = POWER_BUFFER_TYPE_ABSOLUTE_SIZE;

‎libs/libarchfpga/src/read_xml_arch_file.cpp‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -4439,25 +4439,25 @@ static std::vector<t_arch_switch_inf> process_switches(pugi::xml_node Parent,
44394439
/* As noted above, due to their configuration of pass transistors feeding into a buffer,
44404440
* only multiplexers and tristate buffers have an internal capacitance element. */
44414441

4442-
SwitchType type = SwitchType::MUX;
4442+
e_switch_type type = e_switch_type::MUX;
44434443
if (0 == strcmp(type_name, "mux")) {
4444-
type = SwitchType::MUX;
4444+
type = e_switch_type::MUX;
44454445
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Cinternal", "Tdel", "buf_size", "power_buf_size", "mux_trans_size"}, " with type '"s + type_name + "'"s, loc_data);
44464446

44474447
} else if (0 == strcmp(type_name, "tristate")) {
4448-
type = SwitchType::TRISTATE;
4448+
type = e_switch_type::TRISTATE;
44494449
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Cinternal", "Tdel", "buf_size", "power_buf_size"}, " with type '"s + type_name + "'"s, loc_data);
44504450

44514451
} else if (0 == strcmp(type_name, "buffer")) {
4452-
type = SwitchType::BUFFER;
4452+
type = e_switch_type::BUFFER;
44534453
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel", "buf_size", "power_buf_size"}, " with type '"s + type_name + "'"s, loc_data);
44544454

44554455
} else if (0 == strcmp(type_name, "pass_gate")) {
4456-
type = SwitchType::PASS_GATE;
4456+
type = e_switch_type::PASS_GATE;
44574457
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel"}, " with type '"s + type_name + "'"s, loc_data);
44584458

44594459
} else if (0 == strcmp(type_name, "short")) {
4460-
type = SwitchType::SHORT;
4460+
type = e_switch_type::SHORT;
44614461
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel"}, " with type "s + type_name + "'"s, loc_data);
44624462
} else {
44634463
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
@@ -4473,7 +4473,7 @@ static std::vector<t_arch_switch_inf> process_switches(pugi::xml_node Parent,
44734473
// architecture without Cinternal without breaking the program flow.
44744474
ReqOpt CINTERNAL_REQD = ReqOpt::OPTIONAL;
44754475

4476-
if (arch_switch.type() == SwitchType::SHORT) {
4476+
if (arch_switch.type() == e_switch_type::SHORT) {
44774477
//Cin/Cout are optional on shorts, since they really only have one capacitance
44784478
CIN_REQD = ReqOpt::OPTIONAL;
44794479
COUT_REQD = ReqOpt::OPTIONAL;
@@ -4482,15 +4482,15 @@ static std::vector<t_arch_switch_inf> process_switches(pugi::xml_node Parent,
44824482
arch_switch.Cout = get_attribute(Node, "Cout", loc_data, COUT_REQD).as_float(0);
44834483
arch_switch.Cinternal = get_attribute(Node, "Cinternal", loc_data, CINTERNAL_REQD).as_float(0);
44844484

4485-
if (arch_switch.type() == SwitchType::MUX) {
4485+
if (arch_switch.type() == e_switch_type::MUX) {
44864486
//Only muxes have mux transistors
44874487
arch_switch.mux_trans_size = get_attribute(Node, "mux_trans_size", loc_data, ReqOpt::OPTIONAL).as_float(1);
44884488
} else {
44894489
arch_switch.mux_trans_size = 0.;
44904490
}
44914491

4492-
if (arch_switch.type() == SwitchType::SHORT
4493-
|| arch_switch.type() == SwitchType::PASS_GATE) {
4492+
if (arch_switch.type() == e_switch_type::SHORT
4493+
|| arch_switch.type() == e_switch_type::PASS_GATE) {
44944494
//No buffers
44954495
arch_switch.buf_size_type = BufferSize::ABSOLUTE;
44964496
arch_switch.buf_size = 0.;

‎libs/librrgraph/src/base/check_rr_graph.cpp‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -192,7 +192,7 @@ void check_rr_graph(const RRGraphView& rr_graph,
192192
*/
193193
if ((to_rr_type == e_rr_type::CHANX || to_rr_type == e_rr_type::CHANY)
194194
&& (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY)) {
195-
SwitchType switch_type = rr_graph.rr_switch_inf(RRSwitchId(kv.first)).type();
195+
e_switch_type switch_type = rr_graph.rr_switch_inf(RRSwitchId(kv.first)).type();
196196

197197
VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_graph: node %d has %d redundant connections to node %d of switch type %d (%s)",
198198
inode, kv.second, to_node, kv.first, SWITCH_TYPE_STRINGS[size_t(switch_type)]);
@@ -653,7 +653,7 @@ static void check_rr_edge(const RRGraphView& rr_graph,
653653

654654
int to_fanin = rr_graph.node_fan_in(RRNodeId(to_node));
655655
switch (switch_type) {
656-
case SwitchType::BUFFER:
656+
case e_switch_type::BUFFER:
657657
//Buffer switches are non-configurable, and uni-directional -- they must have only one driver
658658
if (to_fanin != 1) {
659659
std::string msg = "Non-configurable BUFFER type switch must have only one driver. ";
@@ -663,10 +663,10 @@ static void check_rr_edge(const RRGraphView& rr_graph,
663663
VPR_FATAL_ERROR(VPR_ERROR_ROUTE, msg.c_str());
664664
}
665665
break;
666-
case SwitchType::TRISTATE: //Fallthrough
667-
case SwitchType::MUX: //Fallthrough
668-
case SwitchType::PASS_GATE: //Fallthrough
669-
case SwitchType::SHORT: //Fallthrough
666+
case e_switch_type::TRISTATE: //Fallthrough
667+
case e_switch_type::MUX: //Fallthrough
668+
case e_switch_type::PASS_GATE: //Fallthrough
669+
case e_switch_type::SHORT: //Fallthrough
670670
break; //pass
671671
default:
672672
VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Invalid switch type %d", switch_type);

‎libs/librrgraph/src/base/rr_switch.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11

22
#include "rr_switch.h"
33

4-
SwitchType t_rr_switch_inf::type() const {
4+
e_switch_type t_rr_switch_inf::type() const {
55
return type_;
66
}
77

@@ -49,6 +49,6 @@ std::size_t t_rr_switch_inf::Hasher::operator()(const t_rr_switch_inf& s) const
4949
return hash_val;
5050
}
5151

52-
void t_rr_switch_inf::set_type(SwitchType type_val) {
52+
void t_rr_switch_inf::set_type(e_switch_type type_val) {
5353
type_ = type_val;
5454
}

‎libs/librrgraph/src/base/rr_switch.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ struct t_rr_switch_inf {
4646

4747
public:
4848
/// Returns the type of switch
49-
SwitchType type() const;
49+
e_switch_type type() const;
5050

5151
/// Returns true if this switch type isolates its input and output into
5252
/// separate DC-connected subcircuits
@@ -68,8 +68,8 @@ struct t_rr_switch_inf {
6868
};
6969

7070
public:
71-
void set_type(SwitchType type_val);
71+
void set_type(e_switch_type type_val);
7272

7373
private:
74-
SwitchType type_ = SwitchType::INVALID;
74+
e_switch_type type_ = e_switch_type::INVALID;
7575
};

‎libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -2069,23 +2069,23 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
20692069
return uxsd::enum_node_type::UXSD_INVALID;
20702070
}
20712071

2072-
SwitchType from_uxsd_switch_type(uxsd::enum_switch_type type) {
2073-
SwitchType switch_type = SwitchType::INVALID;
2072+
e_switch_type from_uxsd_switch_type(uxsd::enum_switch_type type) {
2073+
e_switch_type switch_type = e_switch_type::INVALID;
20742074
switch (type) {
20752075
case uxsd::enum_switch_type::TRISTATE:
2076-
switch_type = SwitchType::TRISTATE;
2076+
switch_type = e_switch_type::TRISTATE;
20772077
break;
20782078
case uxsd::enum_switch_type::MUX:
2079-
switch_type = SwitchType::MUX;
2079+
switch_type = e_switch_type::MUX;
20802080
break;
20812081
case uxsd::enum_switch_type::PASS_GATE:
2082-
switch_type = SwitchType::PASS_GATE;
2082+
switch_type = e_switch_type::PASS_GATE;
20832083
break;
20842084
case uxsd::enum_switch_type::SHORT:
2085-
switch_type = SwitchType::SHORT;
2085+
switch_type = e_switch_type::SHORT;
20862086
break;
20872087
case uxsd::enum_switch_type::BUFFER:
2088-
switch_type = SwitchType::BUFFER;
2088+
switch_type = e_switch_type::BUFFER;
20892089
break;
20902090
default:
20912091
report_error(
@@ -2095,17 +2095,17 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
20952095
return switch_type;
20962096
}
20972097

2098-
uxsd::enum_switch_type to_uxsd_switch_type(SwitchType type) {
2098+
uxsd::enum_switch_type to_uxsd_switch_type(e_switch_type type) {
20992099
switch (type) {
2100-
case SwitchType::TRISTATE:
2100+
case e_switch_type::TRISTATE:
21012101
return uxsd::enum_switch_type::TRISTATE;
2102-
case SwitchType::MUX:
2102+
case e_switch_type::MUX:
21032103
return uxsd::enum_switch_type::MUX;
2104-
case SwitchType::PASS_GATE:
2104+
case e_switch_type::PASS_GATE:
21052105
return uxsd::enum_switch_type::PASS_GATE;
2106-
case SwitchType::SHORT:
2106+
case e_switch_type::SHORT:
21072107
return uxsd::enum_switch_type::SHORT;
2108-
case SwitchType::BUFFER:
2108+
case e_switch_type::BUFFER:
21092109
return uxsd::enum_switch_type::BUFFER;
21102110
default:
21112111
report_error(

‎libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -652,7 +652,7 @@ static void calculate_average_switch(const RRGraphView& rr_graph, int inode, dou
652652
if (rr_graph.node_type(node) == e_rr_type::CHANX || rr_graph.node_type(node) == e_rr_type::CHANY) {
653653
int switch_index = rr_graph.rr_nodes().edge_switch(edge);
654654

655-
if (rr_graph.rr_switch_inf(RRSwitchId(switch_index)).type() == SwitchType::SHORT) {
655+
if (rr_graph.rr_switch_inf(RRSwitchId(switch_index)).type() == e_switch_type::SHORT) {
656656
num_shorts++;
657657
continue;
658658
}

0 commit comments

Comments
 (0)