Merge remote-tracking branch 'origin/master' into feature-ci-packages

Author: AlexandreSinger

doc/src/vpr/graphics.rst

@@ -81,7 +81,7 @@ The Inter-Cluster Nets and Intra-Cluster Nets options allow the user to choose w
 
     Net Tab
 
-If routing is shown, clicking on a pin or channel wire whill highlight the whole net in magenta. 
+If routing is shown, clicking on a pin or channel wire will highlight the whole net in magenta.
 Multiple nets can be highlighted by pressing ctrl + mouse click.
 
 .. figure:: ../Images/show_nets.gif

libs/libarchfpga/src/arch_util.cpp

@@ -4,6 +4,7 @@
 #include <vector>
 
 #include "logic_types.h"
+#include "physical_types.h"
 #include "vtr_assert.h"
 #include "vtr_list.h"
 #include "vtr_memory.h"
@@ -669,12 +670,12 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
     mem_pb_type->modes[0].parent_pb_type = mem_pb_type;
     mem_pb_type->modes[0].index = 0;
     mem_pb_type->modes[0].mode_power = new t_mode_power();
-    num_pb = OPEN;
+    num_pb = ARCH_FPGA_UNDEFINED_VAL;
     for (i = 0; i < mem_pb_type->num_ports; i++) {
         if (mem_pb_type->ports[i].port_class != nullptr
             && strstr(mem_pb_type->ports[i].port_class, "data")
                    == mem_pb_type->ports[i].port_class) {
-            if (num_pb == OPEN) {
+            if (num_pb == ARCH_FPGA_UNDEFINED_VAL) {
                 num_pb = mem_pb_type->ports[i].num_pins;
             } else if (num_pb != mem_pb_type->ports[i].num_pins) {
                 archfpga_throw(get_arch_file_name(), 0,
@@ -1206,7 +1207,7 @@ void setup_pin_classes(t_physical_tile_type* type) {
     int num_class;
 
     for (int i = 0; i < type->num_pins; i++) {
-        type->pin_class.push_back(OPEN);
+        type->pin_class.push_back(ARCH_FPGA_UNDEFINED_VAL);
         type->is_ignored_pin.push_back(true);
         type->is_pin_global.push_back(true);
     }
@@ -1229,10 +1230,10 @@ void setup_pin_classes(t_physical_tile_type* type) {
                     class_inf.equivalence = port.equivalent;
 
                     if (port.type == IN_PORT) {
-                        class_inf.type = RECEIVER;
+                        class_inf.type = e_pin_type::RECEIVER;
                     } else {
                         VTR_ASSERT(port.type == OUT_PORT);
-                        class_inf.type = DRIVER;
+                        class_inf.type = e_pin_type::DRIVER;
                     }
 
                     for (int k = 0; k < port.num_pins; ++k) {
@@ -1263,10 +1264,10 @@ void setup_pin_classes(t_physical_tile_type* type) {
                         class_inf.equivalence = port.equivalent;
 
                         if (port.type == IN_PORT) {
-                            class_inf.type = RECEIVER;
+                            class_inf.type = e_pin_type::RECEIVER;
                         } else {
                             VTR_ASSERT(port.type == OUT_PORT);
-                            class_inf.type = DRIVER;
+                            class_inf.type = e_pin_type::DRIVER;
                         }
 
                         type->pin_class[pin_count] = num_class;

libs/libarchfpga/src/parse_switchblocks.cpp

@@ -177,26 +177,26 @@ static t_wireconn_inf parse_wireconn_inline(pugi::xml_node node,
     parse_num_conns(char_prop, wc);
 
     // get from type
-    char_prop = get_attribute(node, "from_type", loc_data, from_to_required).value();
-    if (!can_skip_from_or_to) {
+    char_prop = get_attribute(node, "from_type", loc_data, from_to_required).as_string();
+    if (*char_prop) { // if from_to_required is ReqOpt::REQUIRED, char_prop is definitely not null. Otherwise, it's optional and should be null checked.
         parse_comma_separated_wire_types(char_prop, wc.from_switchpoint_set);
     }
 
     // get to type
-    char_prop = get_attribute(node, "to_type", loc_data, from_to_required).value();
-    if (!can_skip_from_or_to) {
+    char_prop = get_attribute(node, "to_type", loc_data, from_to_required).as_string();
+    if (*char_prop) {
         parse_comma_separated_wire_types(char_prop, wc.to_switchpoint_set);
     }
 
     // get the source wire point
-    char_prop = get_attribute(node, "from_switchpoint", loc_data, from_to_required).value();
-    if (!can_skip_from_or_to) {
+    char_prop = get_attribute(node, "from_switchpoint", loc_data, from_to_required).as_string();
+    if (*char_prop) {
         parse_comma_separated_wire_points(char_prop, wc.from_switchpoint_set);
     }
 
     // get the destination wire point
-    char_prop = get_attribute(node, "to_switchpoint", loc_data, from_to_required).value();
-    if (!can_skip_from_or_to) {
+    char_prop = get_attribute(node, "to_switchpoint", loc_data, from_to_required).as_string();
+    if (*char_prop) {
         parse_comma_separated_wire_points(char_prop, wc.to_switchpoint_set);
     }
 

libs/libarchfpga/src/physical_types.cpp

@@ -1,4 +1,5 @@
 #include "physical_types.h"
+#include "arch_types.h"
 #include "vtr_math.h"
 #include "vtr_util.h"
 #include "vtr_log.h"
@@ -164,17 +165,17 @@ int t_physical_tile_type::get_sub_tile_loc_from_pin(int pin_num) const {
         }
     }
 
-    return OPEN;
+    return ARCH_FPGA_UNDEFINED_VAL;
 }
 
 bool t_physical_tile_type::is_empty() const {
     return name == std::string(EMPTY_BLOCK_NAME);
 }
 
 int t_physical_tile_type::find_pin(std::string_view port_name, int pin_index_in_port) const {
-    int ipin = OPEN;
+    int ipin = ARCH_FPGA_UNDEFINED_VAL;
     int port_base_ipin = 0;
-    int num_port_pins = OPEN;
+    int num_port_pins = ARCH_FPGA_UNDEFINED_VAL;
     int pin_offset = 0;
 
     bool port_found = false;
@@ -197,7 +198,7 @@ int t_physical_tile_type::find_pin(std::string_view port_name, int pin_index_in_
         pin_offset += sub_tile.num_phy_pins;
     }
 
-    if (num_port_pins != OPEN) {
+    if (num_port_pins != ARCH_FPGA_UNDEFINED_VAL) {
         VTR_ASSERT(pin_index_in_port < num_port_pins);
 
         ipin = port_base_ipin + pin_index_in_port + pin_offset;
@@ -207,14 +208,14 @@ int t_physical_tile_type::find_pin(std::string_view port_name, int pin_index_in_
 }
 
 int t_physical_tile_type::find_pin_class(std::string_view port_name, int pin_index_in_port, e_pin_type pin_type) const {
-    int iclass = OPEN;
+    int iclass = ARCH_FPGA_UNDEFINED_VAL;
 
     int ipin = find_pin(port_name, pin_index_in_port);
 
-    if (ipin != OPEN) {
+    if (ipin != ARCH_FPGA_UNDEFINED_VAL) {
         iclass = pin_class[ipin];
 
-        if (iclass != OPEN) {
+        if (iclass != ARCH_FPGA_UNDEFINED_VAL) {
             VTR_ASSERT(class_inf[iclass].type == pin_type);
         }
     }

libs/libarchfpga/src/physical_types.h

@@ -25,6 +25,7 @@
  * Authors: Jason Luu and Kenneth Kent
  */
 
+#include <cstdint>
 #include <functional>
 #include <utility>
 #include <vector>
@@ -42,6 +43,7 @@
 #include "logic_types.h"
 #include "clock_types.h"
 #include "switchblock_types.h"
+#include "arch_types.h"
 
 #include "vib_inf.h"
 
@@ -163,7 +165,7 @@ struct t_metadata_dict : vtr::flat_map<
 
 /* Pins describe I/O into clustered logic block.
  * A pin may be unconnected, driving a net or in the fanout, respectively. */
-enum e_pin_type {
+enum class e_pin_type : int8_t {
     OPEN = -1,
     DRIVER = 0,
     RECEIVER = 1
@@ -873,9 +875,9 @@ struct t_physical_pin {
  *                  above the base die, the layer_num is 1 and so on.
  */
 struct t_physical_tile_loc {
-    int x = OPEN;
-    int y = OPEN;
-    int layer_num = OPEN;
+    int x = ARCH_FPGA_UNDEFINED_VAL;
+    int y = ARCH_FPGA_UNDEFINED_VAL;
+    int layer_num = ARCH_FPGA_UNDEFINED_VAL;
 
     t_physical_tile_loc() = default;
 
@@ -884,9 +886,9 @@ struct t_physical_tile_loc {
         , y(y_val)
         , layer_num(layer_num_val) {}
 
-    // Returns true if this type location layer_num/x/y is not equal to OPEN
+    // Returns true if this type location layer_num/x/y is not equal to ARCH_FPGA_UNDEFINED_VAL
     operator bool() const {
-        return !(x == OPEN || y == OPEN || layer_num == OPEN);
+        return !(x == ARCH_FPGA_UNDEFINED_VAL || y == ARCH_FPGA_UNDEFINED_VAL || layer_num == ARCH_FPGA_UNDEFINED_VAL);
     }
 };
 
@@ -1369,7 +1371,7 @@ class t_pb_graph_node {
      * There is a root-level pb_graph_node assigned to each logical type. Each logical type can contain multiple primitives.
      * If this pb_graph_node is associated with a primitive, a unique number is assigned to it within the logical block level.
      */
-    int primitive_num = OPEN;
+    int primitive_num = ARCH_FPGA_UNDEFINED_VAL;
 
     /* Contains a collection of mode indices that cannot be used as they produce conflicts during VPR packing stage
      *
@@ -1578,7 +1580,7 @@ class t_pb_graph_edge {
     int* pack_pattern_indices;
     bool infer_pattern;
 
-    int switch_type_idx = OPEN; /* architecture switch id of the edge - used when flat_routing is enabled */
+    int switch_type_idx = ARCH_FPGA_UNDEFINED_VAL; /* architecture switch id of the edge - used when flat_routing is enabled */
 
     // class member functions
   public:

libs/libarchfpga/src/physical_types_util.cpp

@@ -1,4 +1,6 @@
 #include <numeric>
+#include "arch_types.h"
+#include "physical_types.h"
 #include "vtr_assert.h"
 #include "vtr_util.h"
 
@@ -182,8 +184,8 @@ static t_pin_inst_port block_type_pin_index_to_pin_inst(t_physical_tile_type_ptr
     pin_inst_port.logical_block_index = logical_num;
     pin_inst_port.pb_type_idx = pb_type_idx;
     pin_inst_port.pin_physical_num = pin_physical_num;
-    pin_inst_port.port_index = OPEN;
-    pin_inst_port.pin_index_in_port = OPEN;
+    pin_inst_port.port_index = ARCH_FPGA_UNDEFINED_VAL;
+    pin_inst_port.pin_index_in_port = ARCH_FPGA_UNDEFINED_VAL;
 
     if (is_flat && logical_num != -1) {
         auto pb_pin = get_pb_pin_from_pin_physical_num(type, pin_physical_num);
@@ -200,8 +202,8 @@ static t_pin_inst_port block_type_pin_index_to_pin_inst(t_physical_tile_type_ptr
             }
         }
     }
-    VTR_ASSERT(pin_inst_port.port_index != OPEN);
-    VTR_ASSERT(pin_inst_port.pin_index_in_port != OPEN);
+    VTR_ASSERT(pin_inst_port.port_index != ARCH_FPGA_UNDEFINED_VAL);
+    VTR_ASSERT(pin_inst_port.pin_index_in_port != ARCH_FPGA_UNDEFINED_VAL);
     return pin_inst_port;
 }
 
@@ -435,7 +437,7 @@ int get_sub_tile_physical_pin(int sub_tile_index,
 
 int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_tile,
                                               t_logical_block_type_ptr logical_block) {
-    int sub_tile_index = OPEN;
+    int sub_tile_index = ARCH_FPGA_UNDEFINED_VAL;
     for (const auto& sub_tile : physical_tile->sub_tiles) {
         auto eq_sites = sub_tile.equivalent_sites;
         auto it = std::find(eq_sites.begin(), eq_sites.end(), logical_block);
@@ -444,7 +446,7 @@ int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_
         }
     }
 
-    if (sub_tile_index == OPEN) {
+    if (sub_tile_index == ARCH_FPGA_UNDEFINED_VAL) {
         archfpga_throw(__FILE__, __LINE__,
                        "Found no instances of logical block type '%s' within physical tile type '%s'. ",
                        logical_block->name.c_str(), physical_tile->name.c_str());
@@ -458,7 +460,7 @@ int get_physical_pin(t_physical_tile_type_ptr physical_tile,
                      int pin) {
     int sub_tile_index = get_logical_block_physical_sub_tile_index(physical_tile, logical_block);
 
-    if (sub_tile_index == OPEN) {
+    if (sub_tile_index == ARCH_FPGA_UNDEFINED_VAL) {
         archfpga_throw(__FILE__, __LINE__,
                        "Couldn't find the corresponding physical tile type pin of the logical block type pin %d.",
                        pin);
@@ -471,7 +473,7 @@ int get_physical_pin(t_physical_tile_type_ptr physical_tile,
 int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_tile,
                                               t_logical_block_type_ptr logical_block,
                                               int sub_tile_capacity) {
-    int sub_tile_index = OPEN;
+    int sub_tile_index = ARCH_FPGA_UNDEFINED_VAL;
     for (const auto& sub_tile : physical_tile->sub_tiles) {
         auto eq_sites = sub_tile.equivalent_sites;
         auto it = std::find(eq_sites.begin(), eq_sites.end(), logical_block);
@@ -482,7 +484,7 @@ int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_
         }
     }
 
-    if (sub_tile_index == OPEN) {
+    if (sub_tile_index == ARCH_FPGA_UNDEFINED_VAL) {
         archfpga_throw(__FILE__, __LINE__,
                        "Found no instances of logical block type '%s' within physical tile type '%s'. ",
                        logical_block->name.c_str(), physical_tile->name.c_str());
@@ -528,7 +530,7 @@ int get_physical_pin_at_sub_tile_location(t_physical_tile_type_ptr physical_tile
     VTR_ASSERT(pin < physical_tile->num_pins);
     int sub_tile_index = get_logical_block_physical_sub_tile_index(physical_tile, logical_block, sub_tile_capacity);
 
-    if (sub_tile_index == OPEN) {
+    if (sub_tile_index == ARCH_FPGA_UNDEFINED_VAL) {
         archfpga_throw(__FILE__, __LINE__,
                        "Couldn't find the corresponding physical tile type pin of the logical block type pin %d.",
                        pin);
@@ -610,7 +612,7 @@ bool is_opin(int ipin, t_physical_tile_type_ptr type) {
 
     int iclass = type->pin_class[ipin];
 
-    if (type->class_inf[iclass].type == DRIVER)
+    if (type->class_inf[iclass].type == e_pin_type::DRIVER)
         return true;
     else
         return false;
@@ -895,7 +897,7 @@ int get_tile_class_max_ptc(t_physical_tile_type_ptr tile, bool is_flat) {
 /** get information given pin physical number **/
 std::tuple<const t_sub_tile*, int> get_sub_tile_from_pin_physical_num(t_physical_tile_type_ptr physical_tile, int physical_num) {
     const t_sub_tile* target_sub_tile = nullptr;
-    int target_sub_tile_cap = OPEN;
+    int target_sub_tile_cap = ARCH_FPGA_UNDEFINED_VAL;
 
     bool pin_on_tile = is_pin_on_tile(physical_tile, physical_num);
 
@@ -926,7 +928,7 @@ t_logical_block_type_ptr get_logical_block_from_pin_physical_num(t_physical_tile
     t_logical_block_type_ptr logical_block = nullptr;
 
     std::tie(sub_tile, sub_tile_cap) = get_sub_tile_from_pin_physical_num(physical_tile, physical_num);
-    VTR_ASSERT(sub_tile_cap != OPEN);
+    VTR_ASSERT(sub_tile_cap != ARCH_FPGA_UNDEFINED_VAL);
 
     for (auto logical_block_pin_range_pair : sub_tile->intra_pin_range[sub_tile_cap]) {
         if (physical_num >= logical_block_pin_range_pair.second.low) {
@@ -1189,7 +1191,7 @@ int get_pb_pin_physical_num(t_physical_tile_type_ptr physical_tile,
                             t_logical_block_type_ptr logical_block,
                             int relative_cap,
                             const t_pb_graph_pin* pin) {
-    int pin_physical_num = OPEN;
+    int pin_physical_num = ARCH_FPGA_UNDEFINED_VAL;
     if (pin->is_root_block_pin()) {
         pin_physical_num = get_physical_pin_at_sub_tile_location(physical_tile,
                                                                  logical_block,
@@ -1264,12 +1266,12 @@ bool intra_tile_nodes_connected(t_physical_tile_type_ptr physical_type,
         const t_sub_tile* from_sub_tile;
         int from_sub_tile_rel_cap;
         std::tie(from_sub_tile, from_sub_tile_rel_cap) = get_sub_tile_from_pin_physical_num(physical_type, pin_physical_num);
-        VTR_ASSERT(from_sub_tile != nullptr && from_sub_tile_rel_cap != OPEN);
+        VTR_ASSERT(from_sub_tile != nullptr && from_sub_tile_rel_cap != ARCH_FPGA_UNDEFINED_VAL);
 
         const t_sub_tile* to_sub_tile;
         int to_sub_tile_rel_cap;
         std::tie(to_sub_tile, to_sub_tile_rel_cap) = get_sub_tile_from_class_physical_num(physical_type, sink_physical_num);
-        VTR_ASSERT(to_sub_tile != nullptr && to_sub_tile_rel_cap != OPEN);
+        VTR_ASSERT(to_sub_tile != nullptr && to_sub_tile_rel_cap != ARCH_FPGA_UNDEFINED_VAL);
 
         return (from_sub_tile_rel_cap == to_sub_tile_rel_cap) && (from_sub_tile == to_sub_tile);