[test] debug

Author: tangxifan

vtr_flow/arch/timing/k6_frac_N10_tileable_4add_2chains_depop50_supertile_mem20K_22nm.xml

@@ -148,11 +148,11 @@
         <output name="dataout" num_pins="74"/>
         <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
         <pinlocations pattern="custom">
-          <loc side="top">mult_27.datain[72:73] mult_27.dataout[72:73]</loc>
-          <loc side="right" yoffset="0">mult_27.datain[0:17] mult_27.dataout[0:17]</loc>
-          <loc side="right" yoffset="1">mult_27.datain[18:35] mult_27.dataout[18:35]</loc>
-          <loc side="right" yoffset="2">mult_27.datain[36:53] mult_27.dataout[36:53]</loc>
-          <loc side="right" yoffset="3">mult_27.datain[54:71] mult_27.dataout[54:71]</loc>
+          <loc side="top">mult_27.datain[72:73] mult_27.dataout[40:73]</loc>
+          <loc side="right" yoffset="0">mult_27.datain[0:17] mult_27.dataout[0:9] mult_27.dataout</loc>
+          <loc side="right" yoffset="1">mult_27.datain[18:35] mult_27.dataout[10:19]</loc>
+          <loc side="right" yoffset="2">mult_27.datain[36:53] mult_27.dataout[20:29]</loc>
+          <loc side="right" yoffset="3">mult_27.datain[54:71] mult_27.dataout[30:39]</loc>
           <loc side="bottom"/>
         </pinlocations>
       </sub_tile>
@@ -231,8 +231,14 @@
     <direct name="direct_left_3" from_pin="clb.O[19:15]" to_pin="clb.I3[14:10]" x_offset="-1" y_offset="0" z_offset="0"/>
     <direct name="direct_left_4" from_pin="clb.O[39:35]" to_pin="clb.I4[14:10]" x_offset="-1" y_offset="0" z_offset="0"/>
     <!-- Direct connect from MULT to RAM --> 
-    <direct name="direct_mult2ram0" from_pin="mult_memory.dataout[39:0]" to_pin="mult_memory.data[39:0]" x_offset="0" y_offset="0" z_offset="1"/>
-    <direct name="direct_mult2ram1" from_pin="mult_memory.dataout[39:0]" to_pin="mult_memory.data[39:0]" x_offset="0" y_offset="0" z_offset="2"/>
+    <direct name="direct_mult2ram0" from_pin="mult_memory.dataout[9:0]" to_pin="mult_memory.data[9:0]" x_offset="0" y_offset="0" z_offset="1"/>
+    <direct name="direct_mult2ram0" from_pin="mult_memory.dataout[19:10]" to_pin="mult_memory.data[19:10]" x_offset="0" y_offset="0" z_offset="1"/>
+    <direct name="direct_mult2ram0" from_pin="mult_memory.dataout[29:20]" to_pin="mult_memory.data[29:20]" x_offset="0" y_offset="0" z_offset="1"/>
+    <direct name="direct_mult2ram0" from_pin="mult_memory.dataout[39:30]" to_pin="mult_memory.data[39:30]" x_offset="0" y_offset="0" z_offset="1"/>
+    <direct name="direct_mult2ram1" from_pin="mult_memory.dataout[9:0]" to_pin="mult_memory.data[9:0]" x_offset="0" y_offset="0" z_offset="2"/>
+    <direct name="direct_mult2ram1" from_pin="mult_memory.dataout[19:10]" to_pin="mult_memory.data[19:10]" x_offset="0" y_offset="0" z_offset="2"/>
+    <direct name="direct_mult2ram1" from_pin="mult_memory.dataout[29:20]" to_pin="mult_memory.data[29:20]" x_offset="0" y_offset="0" z_offset="2"/>
+    <direct name="direct_mult2ram1" from_pin="mult_memory.dataout[39:30]" to_pin="mult_memory.data[39:30]" x_offset="0" y_offset="0" z_offset="2"/>
   </directlist>
   <complexblocklist>
     <!-- Define I/O pads begin -->