libarchfpga: add secondary models to t_pb_type and t_pb_graph_node

lpawelcz · lpawelcz · commit 90dd8aa2a938 · 2022-12-09T09:03:19.000+01:00
Introduce secondary t_model and t_port to t_pb_types
and secondary input/output/clock_pins in t_pb_graph_node.
Also fill those fields with data required for processing.

Signed-off-by: Pawel Czarnecki &lt;pczarnecki@antmicro.com&gt;
diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp
@@ -326,6 +326,8 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) {
                 delete[] pb_graph_node->input_pins[i][j].parent_pin_class;
         }
         delete[] pb_graph_node->input_pins[i];
+        if (pb_graph_node->has_secondary)
+            delete[] pb_graph_node->input_pins_sec[i];
     }
     for (i = 0; i < pb_graph_node->num_output_ports; i++) {
         for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) {
@@ -343,19 +345,29 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) {
                 delete[] pb_graph_node->output_pins[i][j].num_connectable_primitive_input_pins;
         }
         delete[] pb_graph_node->output_pins[i];
+        if (pb_graph_node->has_secondary)
+            delete[] pb_graph_node->output_pins_sec[i];
     }
     for (i = 0; i < pb_graph_node->num_clock_ports; i++) {
         for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) {
             if (pb_graph_node->clock_pins[i][j].parent_pin_class)
                 delete[] pb_graph_node->clock_pins[i][j].parent_pin_class;
         }
         delete[] pb_graph_node->clock_pins[i];
+        if (pb_graph_node->has_secondary)
+            delete[] pb_graph_node->clock_pins_sec[i];
     }
 
     delete[] pb_graph_node->input_pins;
     delete[] pb_graph_node->output_pins;
     delete[] pb_graph_node->clock_pins;
 
+    if (pb_graph_node->has_secondary) {
+        delete[] pb_graph_node->input_pins_sec;
+        delete[] pb_graph_node->output_pins_sec;
+        delete[] pb_graph_node->clock_pins_sec;
+    }
+
     delete[] pb_graph_node->num_input_pins;
     delete[] pb_graph_node->num_output_pins;
     delete[] pb_graph_node->num_clock_pins;
@@ -472,14 +484,22 @@ static void free_pb_type(t_pb_type* pb_type) {
 
     for (int i = 0; i < pb_type->num_ports; ++i) {
         vtr::free(pb_type->ports[i].name);
+        if (pb_type->class_type == LATCH_CLASS)
+            vtr::free(pb_type->ports_sec[i].name);
         if (pb_type->ports[i].port_class) {
             vtr::free(pb_type->ports[i].port_class);
+            if (pb_type->class_type == LATCH_CLASS)
+                vtr::free(pb_type->ports_sec[i].port_class);
         }
         if (pb_type->ports[i].port_power) {
             vtr::free(pb_type->ports[i].port_power);
+            if (pb_type->class_type == LATCH_CLASS)
+                vtr::free(pb_type->ports_sec[i].port_power);
         }
     }
     vtr::free(pb_type->ports);
+    if (pb_type->class_type == LATCH_CLASS)
+        vtr::free(pb_type->ports_sec);
 }
 
 t_port* findPortByName(const char* name, t_pb_type* pb_type, int* high_index, int* low_index) {
@@ -622,6 +642,35 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
             copy->ports[i].port_power->buffer_type = POWER_BUFFER_TYPE_NONE;
         }
     }
+    // Special case for latch - fill secondary data fields
+    if (pb_type->class_type == LATCH_CLASS) {
+        copy->num_ports_sec = pb_type->num_ports;
+        copy->ports_sec = (t_port*)vtr::calloc(pb_type->num_ports, sizeof(t_port));
+        for (i = 0; i < pb_type->num_ports; i++) {
+            copy->ports_sec[i].is_clock = pb_type->ports[i].is_clock;
+            copy->ports_sec[i].model_port = pb_type->ports[i].model_port;
+            copy->ports_sec[i].type = pb_type->ports[i].type;
+            copy->ports_sec[i].num_pins = pb_type->ports[i].num_pins;
+            copy->ports_sec[i].parent_pb_type = copy;
+            copy->ports_sec[i].name = vtr::strdup(pb_type->ports[i].name);
+            copy->ports_sec[i].port_class = vtr::strdup(pb_type->ports[i].port_class);
+            copy->ports_sec[i].port_index_by_type = pb_type->ports[i].port_index_by_type;
+            copy->ports_sec[i].index = pb_type->ports[i].index;
+            copy->ports_sec[i].absolute_first_pin_index = pb_type->ports[i].absolute_first_pin_index;
+
+            copy->ports_sec[i].port_power = (t_port_power*)vtr::calloc(1,
+                                                                       sizeof(t_port_power));
+            //Defaults
+            if (copy->pb_type_power->estimation_method == POWER_METHOD_AUTO_SIZES) {
+                copy->ports_sec[i].port_power->wire_type = POWER_WIRE_TYPE_AUTO;
+                copy->ports_sec[i].port_power->buffer_type = POWER_BUFFER_TYPE_AUTO;
+            } else if (copy->pb_type_power->estimation_method
+                       == POWER_METHOD_SPECIFY_SIZES) {
+                copy->ports_sec[i].port_power->wire_type = POWER_WIRE_TYPE_IGNORED;
+                copy->ports_sec[i].port_power->buffer_type = POWER_BUFFER_TYPE_NONE;
+            }
+        }
+    }
 
     copy->annotations = (t_pin_to_pin_annotation*)vtr::calloc(pb_type->num_annotations, sizeof(t_pin_to_pin_annotation));
     copy->num_annotations = pb_type->num_annotations;
diff --git a/libs/libarchfpga/src/physical_types.cpp b/libs/libarchfpga/src/physical_types.cpp
@@ -4,6 +4,7 @@
 #include "vtr_log.h"
 
 #include "arch_util.h"
+#include "arch_types.h"
 
 static bool switch_type_is_buffered(SwitchType type);
 static bool switch_type_is_configurable(SwitchType type);
@@ -194,6 +195,131 @@ std::string t_pb_graph_node::hierarchical_type_name() const {
     return vtr::join(names.rbegin(), names.rend(), "/");
 }
 
+void t_pb_graph_node::update_pins() {
+    int i, j, i_input = 0, i_output = 0, i_clockport = 0;
+    t_port* pb_type_ports = pb_type->ports_sec;
+
+    VTR_ASSERT(this->has_secondary == false);
+    this->has_secondary = true;
+
+    int pin_count_in_cluster;
+    for (i = 0; i < this->pb_type->num_ports; i++) {
+        if (pb_type_ports[i].model_port) {
+            VTR_ASSERT(this->pb_type->num_modes == 0);
+        } else {
+            VTR_ASSERT(this->pb_type->num_modes != 0 || pb_type_ports[i].is_clock);
+        }
+        if (pb_type_ports[i].type == IN_PORT && !pb_type_ports[i].is_clock) {
+            this->input_pins_sec = new t_pb_graph_pin* [this->num_input_ports] { nullptr };
+            this->input_pins_sec[i_input] = new t_pb_graph_pin[pb_type_ports[i].num_pins];
+            for (j = 0; j < pb_type_ports[i].num_pins; j++) {
+                this->input_pins_sec[i_input][j].pin_number = j;
+                this->input_pins_sec[i_input][j].port = &pb_type_ports[i];
+                this->input_pins_sec[i_input][j].parent_node = this;
+                this->input_pins_sec[i_input][j].pin_count_in_cluster = this->input_pins[i_input][j].pin_count_in_cluster;
+                this->input_pins_sec[i_input][j].parent_pin_class = this->input_pins[i_input][j].parent_pin_class;
+                if (this->pb_type->blif_model != nullptr) {
+                    if (strcmp(this->pb_type->blif_model, MODEL_OUTPUT) == 0) {
+                        this->input_pins_sec[i_input][j].type = PB_PIN_OUTPAD;
+                    } else if (this->num_clock_ports != 0) {
+                        this->input_pins_sec[i_input][j].type = PB_PIN_SEQUENTIAL;
+                    } else {
+                        this->input_pins_sec[i_input][j].type = PB_PIN_TERMINAL;
+                    }
+                }
+                pin_count_in_cluster++;
+
+                //Copy timings from primary pins
+                // sequential timing information
+                this->input_pins_sec[i_input][j].tsu = this->input_pins[i_input][j].tsu;
+                this->input_pins_sec[i_input][j].thld = this->input_pins[i_input][j].thld;
+                this->input_pins_sec[i_input][j].tco_min = this->input_pins[i_input][j].tco_min;
+                this->input_pins_sec[i_input][j].tco_max = this->input_pins[i_input][j].tco_max;
+                //this->input_pins_sec[i_input][j].t_pb_graph_pin* associated_clock_pin = nullptr;          /* For sequentail elements, the associated clock */
+
+                // combinational timing information
+                this->input_pins_sec[i_input][j].num_pin_timing = this->input_pins[i_input][j].num_pin_timing;
+                this->input_pins_sec[i_input][j].pin_timing_del_max = this->input_pins[i_input][j].pin_timing_del_max;
+                this->input_pins_sec[i_input][j].pin_timing_del_min = this->input_pins[i_input][j].pin_timing_del_min;
+                this->input_pins_sec[i_input][j].num_pin_timing_del_max_annotated = this->input_pins[i_input][j].num_pin_timing_del_max_annotated;
+                this->input_pins_sec[i_input][j].num_pin_timing_del_min_annotated = this->input_pins[i_input][j].num_pin_timing_del_min_annotated;
+                //this->input_pins_sec[i_input][j].std::vector<t_pb_graph_pin*> pin_timing;  /* timing edge sink pins  [0..num_pin_timing-1]*/
+            }
+            i_input++;
+        } else if (pb_type_ports[i].type == OUT_PORT) {
+            this->output_pins_sec = new t_pb_graph_pin* [this->num_input_ports] { nullptr };
+            this->output_pins_sec[i_output] = new t_pb_graph_pin[pb_type_ports[i].num_pins];
+            for (j = 0; j < pb_type_ports[i].num_pins; j++) {
+                this->output_pins_sec[i_output][j].pin_number = j;
+                this->output_pins_sec[i_output][j].port = &pb_type_ports[i];
+                this->output_pins_sec[i_output][j].parent_node = this;
+                this->output_pins_sec[i_output][j].pin_count_in_cluster = this->output_pins[i_output][j].pin_count_in_cluster;
+                this->output_pins_sec[i_output][j].parent_pin_class = this->output_pins[i_output][j].parent_pin_class;
+                this->output_pins_sec[i_output][j].list_of_connectable_input_pin_ptrs = this->output_pins[i_output][j].list_of_connectable_input_pin_ptrs;
+                this->output_pins_sec[i_output][j].num_connectable_primitive_input_pins = this->output_pins[i_output][j].num_connectable_primitive_input_pins;
+                if (this->pb_type->blif_model != nullptr) {
+                    if (strcmp(this->pb_type->blif_model, MODEL_INPUT) == 0) {
+                        this->output_pins_sec[i_output][j].type = PB_PIN_INPAD;
+                    } else if (this->num_clock_ports != 0) {
+                        this->output_pins_sec[i_output][j].type = PB_PIN_SEQUENTIAL;
+                    } else {
+                        this->output_pins_sec[i_output][j].type = PB_PIN_TERMINAL;
+                    }
+                }
+                pin_count_in_cluster++;
+
+                //Copy timings from primary pins
+                // sequential timing information
+                this->output_pins_sec[i_output][j].tsu = this->output_pins[i_output][j].tsu;
+                this->output_pins_sec[i_output][j].thld = this->output_pins[i_output][j].thld;
+                this->output_pins_sec[i_output][j].tco_min = this->output_pins[i_output][j].tco_min;
+                this->output_pins_sec[i_output][j].tco_max = this->output_pins[i_output][j].tco_max;
+                //this->output_pins_sec[i_input][j].t_pb_graph_pin* associated_clock_pin = nullptr;          /* For sequentail elements, the associated clock */
+
+                // combinational timing information
+                this->output_pins_sec[i_output][j].num_pin_timing = this->output_pins[i_output][j].num_pin_timing;
+                this->output_pins_sec[i_output][j].pin_timing_del_max = this->output_pins[i_output][j].pin_timing_del_max;
+                this->output_pins_sec[i_output][j].pin_timing_del_min = this->output_pins[i_output][j].pin_timing_del_min;
+                this->output_pins_sec[i_output][j].num_pin_timing_del_max_annotated = this->output_pins[i_output][j].num_pin_timing_del_max_annotated;
+                this->output_pins_sec[i_output][j].num_pin_timing_del_min_annotated = this->output_pins[i_output][j].num_pin_timing_del_min_annotated;
+                //this->output_pins_sec[i_input][j].std::vector<t_pb_graph_pin*> pin_timing;  /* timing edge sink pins  [0..num_pin_timing-1]*/
+            }
+            i_output++;
+        } else {
+            VTR_ASSERT(pb_type_ports[i].is_clock && pb_type_ports[i].type == IN_PORT);
+            this->clock_pins_sec = new t_pb_graph_pin* [this->num_input_ports] { nullptr };
+            this->clock_pins_sec[i_clockport] = new t_pb_graph_pin[pb_type_ports[i].num_pins];
+            for (j = 0; j < pb_type_ports[i].num_pins; j++) {
+                this->clock_pins_sec[i_clockport][j].pin_number = j;
+                this->clock_pins_sec[i_clockport][j].port = &pb_type_ports[i];
+                this->clock_pins_sec[i_clockport][j].parent_node = this;
+                this->clock_pins_sec[i_clockport][j].pin_count_in_cluster = this->clock_pins[i_clockport][j].pin_count_in_cluster;
+                this->clock_pins_sec[i_clockport][j].parent_pin_class = this->clock_pins[i_clockport][j].parent_pin_class;
+                if (this->pb_type->blif_model != nullptr) {
+                    this->clock_pins_sec[i_clockport][j].type = PB_PIN_CLOCK;
+                }
+                pin_count_in_cluster++;
+
+                //Copy timings from primary pins
+                // sequential timing information
+                this->clock_pins_sec[i_clockport][j].tsu = this->clock_pins[i_clockport][j].tsu;
+                this->clock_pins_sec[i_clockport][j].thld = this->clock_pins[i_clockport][j].thld;
+                this->clock_pins_sec[i_clockport][j].tco_min = this->clock_pins[i_clockport][j].tco_min;
+                this->clock_pins_sec[i_clockport][j].tco_max = this->clock_pins[i_clockport][j].tco_max;
+                //this->clock_pins_sec[i_clockport][j].t_pb_graph_pin* associated_clock_pin = nullptr;          /* For sequentail elements, the associated clock */
+
+                // combinational timing information
+                this->clock_pins_sec[i_clockport][j].num_pin_timing = this->clock_pins[i_clockport][j].num_pin_timing;
+                this->clock_pins_sec[i_clockport][j].pin_timing_del_max = this->clock_pins[i_clockport][j].pin_timing_del_max;
+                this->clock_pins_sec[i_clockport][j].pin_timing_del_min = this->clock_pins[i_clockport][j].pin_timing_del_min;
+                this->clock_pins_sec[i_clockport][j].num_pin_timing_del_max_annotated = this->clock_pins[i_clockport][j].num_pin_timing_del_max_annotated;
+                this->clock_pins_sec[i_clockport][j].num_pin_timing_del_min_annotated = this->clock_pins[i_clockport][j].num_pin_timing_del_min_annotated;
+                //this->clock_pins_sec[i_clockport][j].std::vector<t_pb_graph_pin*> pin_timing;  /* timing edge sink pins  [0..num_pin_timing-1]*/
+            }
+            i_clockport++;
+        }
+    }
+}
 /**
  * t_pb_graph_pin
  */
diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h
@@ -910,9 +910,12 @@ struct t_logical_block_type {
  *      name: name of the physical block type
  *      num_pb: maximum number of instances of this physical block type sharing one parent
  *      blif_model: the string in the blif circuit that corresponds with this pb type
+ *      model: logical model
+ *      model_sec: secondary logical model - used for pb_types matched to 2 available .latch models
  *      class_type: Special library name
  *      modes: Different modes accepted
  *      ports: I/O and clock ports
+ *      ports_sec: secondary I/O and clock ports - used for pb_types matched to 2 available .latch models
  *      num_clock_pins: A count of the total number of clock pins
  *      num_input_pins: A count of the total number of input pins
  *      num_output_pins: A count of the total number of output pins
@@ -927,12 +930,15 @@ struct t_pb_type {
     int num_pb = 0;
     char* blif_model = nullptr;
     t_model* model = nullptr;
+    t_model* model_sec = nullptr;
     enum e_pb_type_class class_type = UNKNOWN_CLASS;
 
     t_mode* modes = nullptr; /* [0..num_modes-1] */
     int num_modes = 0;
     t_port* ports = nullptr; /* [0..num_ports] */
     int num_ports = 0;
+    t_port* ports_sec = nullptr; /* [0..num_ports] */
+    int num_ports_sec = 0;
 
     int num_clock_pins = 0;
     int num_input_pins = 0; /* inputs not including clock pins */
@@ -1166,6 +1172,7 @@ struct t_pin_to_pin_annotation {
 class t_pb_graph_node {
   public:
     t_pb_type* pb_type;
+    bool has_secondary;
 
     int placement_index;
 
@@ -1189,9 +1196,12 @@ class t_pb_graph_node {
      * */
     std::vector<int> illegal_modes;
 
-    t_pb_graph_pin** input_pins;  /* [0..num_input_ports-1] [0..num_port_pins-1]*/
-    t_pb_graph_pin** output_pins; /* [0..num_output_ports-1] [0..num_port_pins-1]*/
-    t_pb_graph_pin** clock_pins;  /* [0..num_clock_ports-1] [0..num_port_pins-1]*/
+    t_pb_graph_pin** input_pins;      /* [0..num_input_ports-1] [0..num_port_pins-1]*/
+    t_pb_graph_pin** output_pins;     /* [0..num_output_ports-1] [0..num_port_pins-1]*/
+    t_pb_graph_pin** clock_pins;      /* [0..num_clock_ports-1] [0..num_port_pins-1]*/
+    t_pb_graph_pin** input_pins_sec;  /* [0..num_input_ports-1] [0..num_port_pins-1]*/
+    t_pb_graph_pin** output_pins_sec; /* [0..num_output_ports-1] [0..num_port_pins-1]*/
+    t_pb_graph_pin** clock_pins_sec;  /* [0..num_clock_ports-1] [0..num_port_pins-1]*/
 
     int num_input_ports;
     int num_output_ports;
@@ -1234,6 +1244,8 @@ class t_pb_graph_node {
     // Returns a string containing the hierarchical type name of the pb_graph_node
     // Ex: clb[0][default]/lab[0][default]/fle[3][n1_lut6]/ble6[0][default]/lut6[0]
     std::string hierarchical_type_name() const;
+
+    void update_pins();
 };
 
 /* Identify pb pin type for timing purposes */
diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp
