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‎vtr_flow/tasks/regression_tests/parmys_reg_basic/vtr_benchmarks/config/config.txt‎

Lines changed: 2 additions & 2 deletions
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@@ -29,8 +29,8 @@ circuit_list_add=stereovision1.v
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circuit_list_add=stereovision2.v
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circuit_list_add=stereovision3.v
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circuit_list_add=LU8PEEng.v
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circuit_list_add=LU32PEEng.v
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circuit_list_add=mcml.v
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#circuit_list_add=LU32PEEng.v
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#circuit_list_add=mcml.v
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# Add architectures to list to sweep
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arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml

‎vtr_flow/tasks/regression_tests/parmys_reg_basic/vtr_benchmarks/config/golden_results.txt‎

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k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 401.81 vpr 909.66 MiB -1 -1 11.78 197920 3 6.49 -1 -1 155540 -1 -1 1498 149 0 179 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 931496 149 182 55416 37075 1 28615 2008 80 80 6400 mult_36 auto 353.2 MiB 20.94 303233 909.7 MiB 47.91 0.37 14.3381 -49440 -14.3381 14.3381 84.89 0.0717821 0.0578119 9.50427 7.84131 100 405910 21 3.90281e+08 1.51617e+08 4.24662e+07 6635.34 147.08 24.2457 20.3899 389407 18 93954 111521 43422718 8861201 15.2309 15.2309 -56666 -15.2309 0 0 5.35781e+07 8371.59 20.80 9.99 2.48836 2.23469
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k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.15 vpr 63.23 MiB -1 -1 0.60 25680 4 0.16 -1 -1 36292 -1 -1 15 11 0 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64744 11 2 303 283 2 80 28 7 7 49 clb auto 24.9 MiB 0.19 267 63.2 MiB 0.02 0.00 1.86151 -149.067 -1.86151 1.77041 0.07 0.000236379 0.000178863 0.0102782 0.00868639 20 457 19 1.07788e+06 808410 52439.0 1070.18 0.08 0.0342395 0.0302305 388 18 286 492 8676 3081 2.28191 2.05156 -171.957 -2.28191 0 0 68696.0 1401.96 0.02 0.03 0.0224724 0.0202938
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k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 617.97 vpr 615.04 MiB -1 -1 55.54 455700 98 88.29 -1 -1 115608 -1 -1 2126 114 45 8 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 629796 114 102 35713 31804 1 16877 2395 56 56 3136 clb auto 342.6 MiB 63.63 225997 547.5 MiB 68.34 0.56 65.4237 -55589.5 -65.4237 65.4237 41.30 0.0898095 0.0706336 10.8204 8.77581 98 330954 34 1.8697e+08 1.42409e+08 2.01848e+07 6436.49 236.06 40.1544 32.9591 308907 21 64100 255615 40561760 9275477 74.7845 74.7845 -69505.8 -74.7845 0 0 2.55970e+07 8162.30 8.94 11.77 3.44705 3.03006
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k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 3889.61 vpr 1.87 GiB -1 -1 173.47 1477392 97 700.79 -1 -1 358556 -1 -1 7412 114 168 32 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1965164 114 102 120062 107871 1 57253 7828 102 102 10404 clb auto 1111.3 MiB 137.08 1023549 1816.3 MiB 246.40 1.71 65.7766 -340242 -65.7766 65.7766 89.63 0.172284 0.148749 24.3054 19.9998 126 1368822 42 6.36957e+08 5.04159e+08 8.56237e+07 8229.88 2304.03 92.6284 77.4782 1308612 21 210475 908838 230850748 55725819 73.7456 73.7456 -469106 -73.7456 0 0 1.08252e+08 10404.8 44.59 69.62 13.5111 11.9172
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k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 4024.09 vpr 1.95 GiB -1 -1 226.76 1239004 25 2675.16 -1 -1 373160 -1 -1 6438 36 159 27 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2045132 36 356 184794 159441 1 63873 7016 95 95 9025 clb auto 1301.0 MiB 102.81 766930 1784.2 MiB 388.02 2.49 43.0057 -282861 -43.0057 43.0057 79.58 0.158924 0.135062 26.2104 21.2126 144 1000444 25 5.4965e+08 4.44764e+08 8.37564e+07 9280.49 371.72 89.0835 73.277 969342 20 218844 498971 94607210 21197683 46.9319 46.9319 -346688 -46.9319 0 0 1.06297e+08 11778.1 34.94 32.42 11.5563 10.142

‎vtr_flow/tasks/regression_tests/vtr_reg_parmys/task_list.txt‎

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regression_tests/vtr_reg_parmys/koios/
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regression_tests/vtr_reg_parmys/vtr_benchmarks/
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regression_tests/vtr_reg_parmys/ultraembedded/
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regression_tests/vtr_reg_parmys/vexriscv/
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regression_tests/vtr_reg_parmys/freecores/

‎vtr_flow/tasks/regression_tests/vtr_reg_parmys/vtr_benchmarks/config/config.txt‎

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#
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############################################
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# Configuration file for running experiments
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##############################################
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# Path to directory of circuits to use
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circuits_dir=benchmarks/verilog
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# Path to directory of architectures to use
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archs_dir=arch/timing
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# Add circuits to list to sweep
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circuit_list_add=arm_core.v
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circuit_list_add=bgm.v
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circuit_list_add=blob_merge.v
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circuit_list_add=boundtop.v
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circuit_list_add=ch_intrinsics.v
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circuit_list_add=diffeq1.v
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circuit_list_add=diffeq2.v
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circuit_list_add=mkDelayWorker32B.v
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circuit_list_add=mkPktMerge.v
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circuit_list_add=mkSMAdapter4B.v
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circuit_list_add=or1200.v
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circuit_list_add=raygentop.v
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circuit_list_add=sha.v
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circuit_list_add=spree.v
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circuit_list_add=stereovision0.v
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circuit_list_add=stereovision1.v
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circuit_list_add=stereovision2.v
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circuit_list_add=stereovision3.v
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circuit_list_add=LU8PEEng.v
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circuit_list_add=LU32PEEng.v
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circuit_list_add=mcml.v
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# Add architectures to list to sweep
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arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
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# Parse info and how to parse
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parse_file=vpr_standard.txt
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# How to parse QoR info
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qor_parse_file=qor_standard.txt
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# Pass requirements
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pass_requirements_file=pass_requirements.txt
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#Script parameters
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script_params=-track_memory_usage -crit_path_router_iterations 100

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