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MohamedElgammal
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Update golden files and add missing ones
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vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters/config/golden_results.txt

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vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt

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vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt

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vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length
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k6_N8_gate_boost_0.2V_22nm.xml Md5Core.v common 561.02 12.61 123256 27 15.63 -1 -1 138616 -1 -1 5890 641 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 1078456 641 128 52347 52475 1 24691 6659 91 91 8281 clb auto 183.27 311456 97.61 0.73 12.9118 -34123.7 -12.9118 12.9118 60.54 0.0612485 0.0531831 9.89888 7.98251 68 446733 33 2.5209e+08 7.10084e+07 3.55803e+07 4296.62 115.29 29.0224 24.2581 413889 15 107844 232243 17228674 3275078 13.5733 13.5733 -36053.1 -13.5733 0 0 4.43124e+07 5351.09 17.45 7.01 3.10422 2.73974 42410 15098 -1 -1 -1 -1
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k6_N8_gate_boost_0.2V_22nm.xml cordic.v common 2.63 0.05 9232 11 0.22 -1 -1 33360 -1 -1 46 54 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 68536 54 51 469 520 1 312 151 10 10 100 clb auto 0.10 2313 0.18 0.00 4.9488 -207.159 -4.9488 4.9488 0.12 0.000597627 0.000481519 0.0596217 0.0487068 50 4972 26 1.91864e+06 554530 264954. 2649.54 0.98 0.208444 0.176477 4461 18 1872 8041 459971 107312 5.4296 5.4296 -231.493 -5.4296 0 0 317040. 3170.40 0.06 0.09 0.0309584 0.0277996 359 359 -1 -1 -1 -1
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k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 607.06 14.22 110532 1 3.85 -1 -1 168832 -1 -1 5784 641 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 1157952 641 128 63843 53443 1 24861 6553 90 90 8100 clb auto 25.54 316995 276.94 1.44 6.22442 -24286.9 -6.22442 6.22442 62.02 0.0532843 0.045816 10.7799 8.54605 74 434562 33 2.53171e+08 7.26417e+07 3.72985e+07 4604.75 143.62 33.4074 27.4978 404856 16 94493 167001 17536749 3023582 5.98868 5.98868 -24820.3 -5.98868 0 0 4.63728e+07 5725.03 21.12 6.61 2.89675 2.52044 43404 3440 12624 36 0 0
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k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 3.94 0.03 9476 4 0.12 -1 -1 32748 -1 -1 42 54 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 68448 54 51 517 516 1 301 147 10 10 100 clb auto 1.26 1956 0.23 0.00 3.71205 -184.501 -3.71205 3.71205 0.12 0.000574395 0.000498369 0.0721433 0.060153 46 4447 39 1.94278e+06 527436 244280. 2442.80 1.22 0.242678 0.20723 3739 19 1588 6261 340386 80664 3.89654 3.89654 -203.39 -3.89654 0 0 298105. 2981.05 0.05 0.08 0.0346354 0.0316723 315 291 60 18 54 18
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k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 625.14 14.11 110688 1 3.82 -1 -1 168784 -1 -1 5776 641 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 1162892 641 128 63843 53443 1 24860 6545 90 90 8100 clb auto 40.93 291391 280.06 1.61 5.37451 -23306.6 -5.37451 5.37451 60.87 0.054596 0.0465628 10.929 8.59823 74 411779 35 2.53845e+08 7.32344e+07 3.72985e+07 4604.75 142.06 34.1954 28.0112 382561 32 106569 186826 20333947 3932009 4.92089 4.92089 -23833.3 -4.92089 0 0 4.63728e+07 5725.03 21.20 9.48 4.82742 4.16577 43450 3440 12624 36 0 0
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k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 3.54 0.04 9428 4 0.12 -1 -1 32784 -1 -1 41 54 0 0 success v8.0.0-3684-g44d092b7d-dirty Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-28T15:22:43 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 68496 54 51 517 516 1 305 146 10 10 100 clb auto 0.90 2002 0.23 0.00 3.55653 -181.169 -3.55653 3.55653 0.13 0.000587628 0.000480292 0.0682492 0.0566937 46 4376 40 1.94854e+06 519798 244280. 2442.80 1.13 0.228573 0.194694 3684 16 1518 5647 297195 70804 3.76303 3.76303 -198.452 -3.76303 0 0 298105. 2981.05 0.06 0.09 0.0400905 0.0367294 314 291 60 18 54 18
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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length
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k6_N8_gate_boost_0.2V_22nm.xml Md5Core.v common 731.58 vpr 959.45 MiB 14.80 133840 -1 -1 27 17.03 -1 -1 138668 -1 -1 5890 641 0 0 success v8.0.0-6703-g3c1ea0885 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-18T20:58:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/golden-bug/vtr-verilog-to-routing 982476 641 128 52347 52475 1 24691 6659 91 91 8281 clb auto 357.0 MiB 178.10 324122 959.4 MiB 78.26 0.62 12.5994 -34588.4 -12.5994 12.5994 66.88 0.0642326 0.0570039 9.26768 7.81878 70 450010 38 2.5209e+08 7.10084e+07 3.65311e+07 4411.44 290.75 41.405 35.9882 428220 16 104824 226074 17650294 3346493 13.6812 13.6812 -36483.3 -13.6812 0 0 4.59210e+07 5545.35 21.10 7.83 3.55648 3.2124 42410 15098 -1 -1 -1 -1
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k6_N8_gate_boost_0.2V_22nm.xml cordic.v common 2.94 vpr 61.41 MiB 0.05 9280 -1 -1 11 0.29 -1 -1 33332 -1 -1 46 54 0 0 success v8.0.0-6703-g3c1ea0885 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-18T20:58:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/golden-bug/vtr-verilog-to-routing 62888 54 51 469 520 1 312 151 10 10 100 clb auto 23.5 MiB 0.14 2353 61.4 MiB 0.06 0.00 5.08149 -205.596 -5.08149 5.08149 0.16 0.000420478 0.000345424 0.0162395 0.0138208 50 5234 25 1.91864e+06 554530 264954. 2649.54 1.16 0.176797 0.157406 4614 22 1947 8386 484081 113201 5.49532 5.49532 -235.774 -5.49532 0 0 317040. 3170.40 0.07 0.11 0.0352896 0.0323964 359 359 -1 -1 -1 -1
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k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 742.93 vpr 1002.32 MiB 14.88 119392 -1 -1 1 4.15 -1 -1 168788 -1 -1 5784 641 0 0 success v8.0.0-6703-g3c1ea0885 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-18T20:58:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/golden-bug/vtr-verilog-to-routing 1026372 641 128 63843 53443 1 24861 6553 90 90 8100 clb auto 410.0 MiB 25.43 306915 990.8 MiB 221.44 1.64 5.52522 -23890 -5.52522 5.52522 69.50 0.0641481 0.0571167 10.7645 9.16992 76 419349 50 2.53171e+08 7.26417e+07 3.80498e+07 4697.50 320.11 53.0525 46.5528 392333 16 95496 170704 16453428 2869400 5.40768 5.40768 -24248.8 -5.40768 0 0 4.69602e+07 5797.55 20.93 6.54 3.62145 3.30431 43404 3440 12624 36 0 0
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k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 4.20 vpr 61.98 MiB 0.05 9332 -1 -1 4 0.19 -1 -1 32712 -1 -1 42 54 0 0 success v8.0.0-6703-g3c1ea0885 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-18T20:58:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/golden-bug/vtr-verilog-to-routing 63464 54 51 517 516 1 301 147 10 10 100 clb auto 24.1 MiB 1.27 2021 62.0 MiB 0.08 0.00 3.81336 -190.838 -3.81336 3.81336 0.15 0.000380268 0.00031708 0.0197698 0.0169928 46 4450 42 1.94278e+06 527436 244280. 2442.80 1.23 0.176425 0.1571 3687 15 1596 6280 306732 73768 3.84465 3.84465 -203.603 -3.84465 0 0 298105. 2981.05 0.10 0.12 0.0432622 0.039967 315 291 60 18 54 18
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k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 609.05 vpr 994.42 MiB 13.36 119288 -1 -1 1 4.04 -1 -1 168660 -1 -1 5776 641 0 0 success v8.0.0-6703-g3c1ea0885 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-18T20:58:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/golden-bug/vtr-verilog-to-routing 1018284 641 128 63843 53443 1 24860 6545 90 90 8100 clb auto 417.3 MiB 41.05 310209 994.4 MiB 252.30 1.56 5.34151 -23794.9 -5.34151 5.34151 71.95 0.0662681 0.0587886 11.1515 9.52557 74 441496 49 2.53845e+08 7.32344e+07 3.72985e+07 4604.75 137.78 33.6275 29.1512 404730 18 108939 190440 20338568 3529267 5.04497 5.04497 -24336.1 -5.04497 0 0 4.63728e+07 5725.03 22.45 8.19 3.76338 3.38807 43450 3440 12624 36 0 0
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k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 4.56 vpr 62.08 MiB 0.05 9280 -1 -1 4 0.14 -1 -1 32788 -1 -1 41 54 0 0 success v8.0.0-6703-g3c1ea0885 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-18T20:58:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/golden-bug/vtr-verilog-to-routing 63572 54 51 517 516 1 301 146 10 10 100 clb auto 24.3 MiB 0.95 2039 62.1 MiB 0.07 0.00 3.52214 -180.139 -3.52214 3.52214 0.15 0.000373477 0.00030284 0.0159338 0.0136629 56 4208 21 1.94854e+06 519798 285865. 2858.65 1.99 0.242192 0.214874 3893 16 1563 6205 362687 85196 3.71763 3.71763 -197.041 -3.71763 0 0 351033. 3510.33 0.11 0.14 0.0517815 0.0478651 314 291 60 18 54 18

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