fixed simple-7series.xml to work with current VPR and arash's VPR. Also added tests

Author: WhiteNinjaZ

vtr_flow/arch/xilinx/simple-7series.xml

@@ -117,6 +117,14 @@
 		</segment>
 
 		<!-- No length 18 horizontal chanels -->
+    <!-- VPR freaks out if this is not included -->
+    <segment axis="x" name="len18_x" freq="0.000000" length="18" type="bidir" Rmetal="101" Cmetal="22.5e-15">
+			<wire_switch name="01"/>
+			<sb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1</sb>
+			<cb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1</cb>
+			<opin_switch name="01"/>
+		</segment>
+
 		<segment axis="y" name="len18_y" freq="0.094736" length="18" type="bidir" Rmetal="101" Cmetal="22.5e-15">
 			<wire_switch name="01"/>
 			<sb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1</sb>
@@ -135,7 +143,7 @@
 			<cb type="pattern">1</cb>
 		</segment>
 
-		<segment axis="x" name="len2_x" freq="0.258064" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+		<segment axis="x" name="len2_x" freq="0.387096" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15">
 			<mux name="0"/>
 			<sb type="pattern">1 1 1</sb>
 			<cb type="pattern">1 1</cb>
@@ -158,7 +166,13 @@
 		</segment>
 
 		<!-- No length 6 horizontal chanels -->
-		<segment axis="y" name="len6_y" freq="0.252631" length="6" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+    <!-- VPR freaks out if this is not included -->
+    <segment axis="x" name="len6_x" freq="0.000000" length="6" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+			<mux name="0"/>
+			<sb type="pattern">1 1 1 1 1 1 1</sb>
+			<cb type="pattern">1 1 1 1 1 1</cb>
+		</segment>
+		<segment axis="y" name="len6_y" freq="0.252633" length="6" type="unidir" Rmetal="101" Cmetal="22.5e-15">
 			<mux name="0"/>
 			<sb type="pattern">1 1 1 1 1 1 1</sb>
 			<cb type="pattern">1 1 1 1 1 1</cb>

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_support/config/config.txt

@@ -0,0 +1,29 @@
+#
+############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=benchmarks/verilog
+
+# Path to directory of architectures to use
+archs_dir=arch/Xilinx
+
+# Add circuits to list to sweep
+circuit_list_add=stereovision3.v
+
+# Add architectures to list to sweep
+arch_list_add=simple-seven-series.xml
+
+############################ The following configurations are not changed and have been checked #####################
+
+# Parse info and how to parse
+parse_file=vpr_standard.txt
+
+# How to parse QoR info
+qor_parse_file=qor_standard.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements.txt
+
+script_params=-track_memory_usage # TODO: Check this ##############################