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Merge pull request #2249 from CAS-Atlantic/improve-reg-tests
Improve reg tests
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‎.github/workflows/test.yml‎

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@@ -178,7 +178,7 @@ jobs:
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{
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name: 'Basic_odin',
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params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DWITH_ODIN=on',
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suite: 'vtr_reg_basic'
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suite: 'vtr_reg_basic_odin'
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},
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{
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name: 'Basic with NO_GRAPHICS',

‎odin_ii/Makefile‎

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# debug
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BUILD_TYPE ?= release
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MAKEFLAGS := -s
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CMAKE_ARGS = -DVTR_IPO_BUILD=off $(CMAKE_PARAMS)
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CMAKE_ARGS = -DVTR_IPO_BUILD=off -DWITH_ODIN=on $(CMAKE_PARAMS)
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BUILD_DIR=../build
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ODIN_BUILD_DIR=$(BUILD_DIR)/odin_ii

‎vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt‎

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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
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k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.80 vpr 62.16 MiB -1 -1 0.23 21952 3 0.05 -1 -1 37108 -1 -1 70 99 1 0 success v8.0.0-6956-gf669015f3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-01-27T02:28:44 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63656 99 130 351 481 1 224 300 13 13 169 clb auto 23.7 MiB 0.04 527 62.2 MiB 0.10 0.00 30 1250 10 3.33e+06 2.22e+06 408126. 2414.95 0.79
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k4_N10_memSize16384_memData64.xml diffeq1.v common 4.74 vpr 66.30 MiB -1 -1 0.34 26676 23 0.30 -1 -1 37692 -1 -1 69 162 0 5 success v8.0.0-6956-gf669015f3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-01-27T02:28:44 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 67888 162 96 1186 1127 1 676 332 13 13 169 clb auto 28.3 MiB 0.14 4471 66.3 MiB 0.13 0.00 54 9470 21 3.33e+06 2.52e+06 696024. 4118.48 2.84
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k4_N10_memSize16384_memData64.xml single_wire.v common 0.35 vpr 59.43 MiB -1 -1 0.05 19896 1 0.01 -1 -1 33124 -1 -1 0 1 0 0 success v8.0.0-6956-gf669015f3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-01-27T02:28:44 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 60860 1 1 1 2 0 1 2 3 3 9 -1 auto 20.6 MiB 0.00 2 59.4 MiB 0.00 0.00 2 2 1 30000 0 1489.46 165.495 0.00

‎vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt‎

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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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k6_N10_mem32K_40nm.xml ch_intrinsics.v common 2.99 vpr 63.55 MiB -1 -1 0.22 21924 3 0.06 -1 -1 36616 -1 -1 69 99 1 0 success v8.0.0-6956-gf669015f3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-01-27T02:28:44 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65072 99 130 343 473 1 230 299 12 12 144 clb auto 24.9 MiB 0.06 592 63.5 MiB 0.13 0.00 1.64429 -113.766 -1.64429 1.64429 0.25 0.000392271 0.000354946 0.0340312 0.0307792 42 1253 12 5.66058e+06 4.26669e+06 330626. 2296.01 1.25 0.188855 0.173963 1081 56 674 909 69958 18408 1.93469 1.93469 -131.89 -1.93469 -0.435251 -0.221714 415849. 2887.84 0.10 0.07 0.0503087 0.0468697
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k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.08 vpr 63.63 MiB -1 -1 0.22 22000 3 0.06 -1 -1 36936 -1 -1 69 99 1 0 success v8.0.0-6956-gf669015f3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-01-27T02:28:44 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65156 99 130 343 473 1 230 299 12 12 144 clb auto 25.1 MiB 0.06 592 63.6 MiB 0.13 0.00 1.64429 -113.766 -1.64429 1.64429 0.25 0.000388017 0.000350874 0.0342309 0.030956 42 1253 12 5.66058e+06 4.26669e+06 330626. 2296.01 1.28 0.187551 0.172575 1081 56 674 909 69958 18408 1.93469 1.93469 -131.89 -1.93469 -0.435251 -0.221714 415849. 2887.84 0.11 0.07 0.051059 0.0474976
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k6_N10_mem32K_40nm.xml diffeq1.v common 6.59 vpr 66.95 MiB -1 -1 0.35 26760 15 0.34 -1 -1 37888 -1 -1 49 162 0 5 success v8.0.0-6956-gf669015f3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-01-27T02:28:44 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 68556 162 96 993 934 1 713 312 16 16 256 mult_36 auto 28.9 MiB 0.19 5824 66.9 MiB 0.36 0.01 19.9533 -1677 -19.9533 19.9533 0.54 0.00150749 0.00137729 0.126685 0.114987 44 11808 35 1.21132e+07 4.62081e+06 665287. 2598.78 2.75 0.527852 0.484329 9456 25 3776 8119 2549621 620254 22.1509 22.1509 -1847.63 -22.1509 0 0 864808. 3378.16 0.22 0.43 0.0904537 0.0845469

‎vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt‎

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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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k6_N10_mem32K_40nm.xml mkPktMerge.v common 12.83 vpr 69.31 MiB -1 -1 0.71 28676 2 0.09 -1 -1 37424 -1 -1 32 311 15 0 success v8.0.0-6956-gf669015f3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-01-27T02:28:44 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 70976 311 156 972 1128 1 953 514 28 28 784 memory auto 31.2 MiB 0.36 8263 69.3 MiB 0.59 0.01 4.10714 -4079.96 -4.10714 4.10714 1.72 0.00214647 0.00185203 0.23994 0.207616 40 13618 30 4.25198e+07 9.94461e+06 2.03169e+06 2591.44 5.22 0.85966 0.771476 12768 27 2728 3251 4233754 1299121 4.07346 4.07346 -4907.34 -4.07346 -19.7517 -0.360359 2.55406e+06 3257.73 0.67 0.81 0.165376 0.152898

‎vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt‎

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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
1+
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
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k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 1.57 vpr 62.44 MiB -1 -1 0.19 21964 3 0.04 -1 -1 36808 -1 -1 70 99 1 0 success v8.0.0-6956-gf669015f3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-01-27T02:28:44 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63936 99 130 351 481 1 224 300 13 13 169 clb auto 24.0 MiB 0.04 530 62.4 MiB 0.10 0.00 28 1586 22 3.33e+06 2.22e+06 384474. 2275.00 0.65

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