Merge pull request #3381 from verilog-to-routing/feature-ci

[Benchmarks] Updated S10 Other Benchmarks

Author: AlexandreSinger

vtr_flow/benchmarks/titan_blif/other_benchmarks/stratix10/murax_stratix10_arch_timing.blif

@@ -1,4 +1,4 @@
-#BLIF OUTPUT: /home/talaeikh/thesis_results/stratix10_final/benchmarks/other_benchmarks/murax/stratix10/quartus2_proj/netlists/murax_symbiflow_stratixiv_arch_timing_adapted_param_lut.blif
+#BLIF OUTPUT: /home/talaeikh/temp21/benchmarks/other_benchmarks/murax/stratix10/quartus2_proj/netlists/murax_symbiflow_stratix10_arch_timing.blif
 
 #MAIN MODEL
 
@@ -18279,7 +18279,52 @@
 
 #SUBCKT MODELS
 
-.model fourteennm_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{4}.port_b_address_width{4}
+.model fourteennm_lcell_comb5
+.inputs \
+    cin \
+    datae \
+    datad \
+    datac \
+    datab \
+    dataa
+.outputs \
+    cout \
+    sumout \
+    combout
+.blackbox
+.end
+
+.model fourteennm_lcell_comb6
+.inputs \
+    cin \
+    datah \
+    datag \
+    dataf \
+    datae \
+    datad \
+    datac \
+    datab \
+    dataa
+.outputs \
+    cout \
+    sumout \
+    combout
+.blackbox
+.end
+
+.model fourteennm_ff
+.inputs \
+    d \
+    sclr \
+    clrn \
+    ena \
+    clk
+.outputs \
+    q
+.blackbox
+.end
+
+.model fourteennm_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{10}.port_b_address_width{10}
 .inputs \
     clk_portbout \
     clk_portbin \
@@ -18306,6 +18351,12 @@
     portbaddr[1] \
     portbaddr[2] \
     portbaddr[3] \
+    portbaddr[4] \
+    portbaddr[5] \
+    portbaddr[6] \
+    portbaddr[7] \
+    portbaddr[8] \
+    portbaddr[9] \
     portaaddrstall \
     portabyteenamasks[0] \
     portabyteenamasks[1] \
@@ -18320,6 +18371,12 @@
     portaaddr[1] \
     portaaddr[2] \
     portaaddr[3] \
+    portaaddr[4] \
+    portaaddr[5] \
+    portaaddr[6] \
+    portaaddr[7] \
+    portaaddr[8] \
+    portaaddr[9] \
     portadatain
 .outputs \
     portbdataout \
@@ -18379,7 +18436,7 @@
 .blackbox
 .end
 
-.model fourteennm_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{10}.port_b_address_width{10}
+.model fourteennm_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{4}.port_b_address_width{4}
 .inputs \
     clk_portbout \
     clk_portbin \
@@ -18406,12 +18463,6 @@
     portbaddr[1] \
     portbaddr[2] \
     portbaddr[3] \
-    portbaddr[4] \
-    portbaddr[5] \
-    portbaddr[6] \
-    portbaddr[7] \
-    portbaddr[8] \
-    portbaddr[9] \
     portaaddrstall \
     portabyteenamasks[0] \
     portabyteenamasks[1] \
@@ -18426,61 +18477,10 @@
     portaaddr[1] \
     portaaddr[2] \
     portaaddr[3] \
-    portaaddr[4] \
-    portaaddr[5] \
-    portaaddr[6] \
-    portaaddr[7] \
-    portaaddr[8] \
-    portaaddr[9] \
     portadatain
 .outputs \
     portbdataout \
     eccstatus[0] \
     eccstatus[1]
 .blackbox
 .end
-
-.model fourteennm_ff
-.inputs \
-    d \
-    sclr \
-    clrn \
-    ena \
-    clk
-.outputs \
-    q
-.blackbox
-.end
-
-.model fourteennm_lcell_comb6
-.inputs \
-    cin \
-    datah \
-    datag \
-    dataf \
-    datae \
-    datad \
-    datac \
-    datab \
-    dataa
-.outputs \
-    cout \
-    sumout \
-    combout
-.blackbox
-.end
-
-.model fourteennm_lcell_comb5
-.inputs \
-    cin \
-    datae \
-    datad \
-    datac \
-    datab \
-    dataa
-.outputs \
-    cout \
-    sumout \
-    combout
-.blackbox
-.end

vtr_flow/benchmarks/titan_blif/other_benchmarks/stratix10/picosoc_stratix10_arch_timing.blif

@@ -1,4 +1,4 @@
-#BLIF OUTPUT: /home/talaeikh/thesis_results/stratix10_final/benchmarks/other_benchmarks/picosoc/stratix10/quartus2_proj/netlists/picosoc_symbiflow_stratixiv_arch_timing_adapted_param_lut.blif
+#BLIF OUTPUT: /home/talaeikh/temp21/benchmarks/other_benchmarks/picosoc/stratix10/quartus2_proj/netlists/picosoc_symbiflow_stratix10_arch_timing.blif
 
 #MAIN MODEL
 
@@ -37729,7 +37729,52 @@
 
 #SUBCKT MODELS
 
-.model fourteennm_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{5}.port_b_address_width{5}
+.model fourteennm_lcell_comb5
+.inputs \
+    cin \
+    datae \
+    datad \
+    datac \
+    datab \
+    dataa
+.outputs \
+    cout \
+    sumout \
+    combout
+.blackbox
+.end
+
+.model fourteennm_lcell_comb6
+.inputs \
+    cin \
+    datah \
+    datag \
+    dataf \
+    datae \
+    datad \
+    datac \
+    datab \
+    dataa
+.outputs \
+    cout \
+    sumout \
+    combout
+.blackbox
+.end
+
+.model fourteennm_ff
+.inputs \
+    d \
+    sclr \
+    clrn \
+    ena \
+    clk
+.outputs \
+    q
+.blackbox
+.end
+
+.model fourteennm_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{11}.port_b_address_width{11}
 .inputs \
     clk_portbout \
     clk_portbin \
@@ -37757,6 +37802,12 @@
     portbaddr[2] \
     portbaddr[3] \
     portbaddr[4] \
+    portbaddr[5] \
+    portbaddr[6] \
+    portbaddr[7] \
+    portbaddr[8] \
+    portbaddr[9] \
+    portbaddr[10] \
     portaaddrstall \
     portabyteenamasks[0] \
     portabyteenamasks[1] \
@@ -37772,6 +37823,12 @@
     portaaddr[2] \
     portaaddr[3] \
     portaaddr[4] \
+    portaaddr[5] \
+    portaaddr[6] \
+    portaaddr[7] \
+    portaaddr[8] \
+    portaaddr[9] \
+    portaaddr[10] \
     portadatain
 .outputs \
     portbdataout \
@@ -37837,7 +37894,7 @@
 .blackbox
 .end
 
-.model fourteennm_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{11}.port_b_address_width{11}
+.model fourteennm_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{5}.port_b_address_width{5}
 .inputs \
     clk_portbout \
     clk_portbin \
@@ -37865,12 +37922,6 @@
     portbaddr[2] \
     portbaddr[3] \
     portbaddr[4] \
-    portbaddr[5] \
-    portbaddr[6] \
-    portbaddr[7] \
-    portbaddr[8] \
-    portbaddr[9] \
-    portbaddr[10] \
     portaaddrstall \
     portabyteenamasks[0] \
     portabyteenamasks[1] \
@@ -37886,61 +37937,10 @@
     portaaddr[2] \
     portaaddr[3] \
     portaaddr[4] \
-    portaaddr[5] \
-    portaaddr[6] \
-    portaaddr[7] \
-    portaaddr[8] \
-    portaaddr[9] \
-    portaaddr[10] \
     portadatain
 .outputs \
     portbdataout \
     eccstatus[0] \
     eccstatus[1]
 .blackbox
 .end
-
-.model fourteennm_ff
-.inputs \
-    d \
-    sclr \
-    clrn \
-    ena \
-    clk
-.outputs \
-    q
-.blackbox
-.end
-
-.model fourteennm_lcell_comb6
-.inputs \
-    cin \
-    datah \
-    datag \
-    dataf \
-    datae \
-    datad \
-    datac \
-    datab \
-    dataa
-.outputs \
-    cout \
-    sumout \
-    combout
-.blackbox
-.end
-
-.model fourteennm_lcell_comb5
-.inputs \
-    cin \
-    datae \
-    datad \
-    datac \
-    datab \
-    dataa
-.outputs \
-    cout \
-    sumout \
-    combout
-.blackbox
-.end