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ponameponame
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skip arithmetic_power for yosys
1 parent ff9ea9c commit 71d52ee

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‎parmys/regression_test/benchmark/task/operators/synthesis_result.json‎

Lines changed: 0 additions & 252 deletions
Original file line numberDiff line numberDiff line change
@@ -2491,144 +2491,6 @@
24912491
"OR": 22,
24922492
"NOT": 12
24932493
},
2494-
"operators/eightbit_arithmetic_power/k6_frac_N10_frac_chain_mem32K_40nm": {
2495-
"test_name": "operators/eightbit_arithmetic_power/k6_frac_N10_frac_chain_mem32K_40nm",
2496-
"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
2497-
"warnings": [
2498-
"wire '\\c' is assigned in a block at regression_test/benchmark/verilog/operators/eightbit_arithmetic_power.v:15.12-15.22.",
2499-
"wire '\\c' is assigned in a block at regression_test/benchmark/verilog/operators/eightbit_arithmetic_power.v:16.18-16.23.",
2500-
"Ignoring module eightbit_arithmetic_power because it contains processes (run 'proc' command first).",
2501-
"Ignoring module eightbit_arithmetic_power because it contains processes (run 'proc' command first).",
2502-
"Ignoring module eightbit_arithmetic_power because it contains processes (run 'proc' command first)."
2503-
],
2504-
"max_rss(MiB)": 25.6,
2505-
"exec_time(ms)": 43.8,
2506-
"elaboration_time(ms)": 0.6,
2507-
"optimization_time(ms)": 0,
2508-
"techmap_time(ms)": 0,
2509-
"synthesis_time(ms)": 2.3,
2510-
"Pi": 10,
2511-
"Po": 8,
2512-
"logic element": 2,
2513-
"generic logic size": 4,
2514-
"Longest Path": 4,
2515-
"Average Path": 4,
2516-
"Estimated LUTs": 8,
2517-
"Total Node": 2,
2518-
"Wires": 34,
2519-
"Wire Bits": 34,
2520-
"Public Wires": 18,
2521-
"Public Wire Bits": 18,
2522-
"Total Cells": 17,
2523-
"MUX": 8,
2524-
"DFFs": [
2525-
"$_DFF_P_ 8"
2526-
],
2527-
"pow": 1
2528-
},
2529-
"operators/eightbit_arithmetic_power/k6_N10_40nm": {
2530-
"test_name": "operators/eightbit_arithmetic_power/k6_N10_40nm",
2531-
"architecture": "k6_N10_40nm.xml",
2532-
"warnings": [
2533-
"wire '\\c' is assigned in a block at regression_test/benchmark/verilog/operators/eightbit_arithmetic_power.v:15.12-15.22.",
2534-
"wire '\\c' is assigned in a block at regression_test/benchmark/verilog/operators/eightbit_arithmetic_power.v:16.18-16.23.",
2535-
"Ignoring module eightbit_arithmetic_power because it contains processes (run 'proc' command first).",
2536-
"Ignoring module eightbit_arithmetic_power because it contains processes (run 'proc' command first).",
2537-
"Ignoring module eightbit_arithmetic_power because it contains processes (run 'proc' command first)."
2538-
],
2539-
"max_rss(MiB)": 15.9,
2540-
"exec_time(ms)": 7.7,
2541-
"elaboration_time(ms)": 1,
2542-
"optimization_time(ms)": 0,
2543-
"techmap_time(ms)": 0.6,
2544-
"synthesis_time(ms)": 3.5,
2545-
"Pi": 10,
2546-
"Po": 8,
2547-
"logic element": 2,
2548-
"generic logic size": 6,
2549-
"Longest Path": 4,
2550-
"Average Path": 4,
2551-
"Estimated LUTs": 6,
2552-
"Total Node": 2,
2553-
"Wires": 34,
2554-
"Wire Bits": 34,
2555-
"Public Wires": 18,
2556-
"Public Wire Bits": 18,
2557-
"Total Cells": 17,
2558-
"MUX": 8,
2559-
"DFFs": [
2560-
"$_DFF_P_ 8"
2561-
],
2562-
"pow": 1
2563-
},
2564-
"operators/eightbit_arithmetic_power/k6_N10_mem32K_40nm": {
2565-
"test_name": "operators/eightbit_arithmetic_power/k6_N10_mem32K_40nm",
2566-
"architecture": "k6_N10_mem32K_40nm.xml",
2567-
"warnings": [
2568-
"wire '\\c' is assigned in a block at regression_test/benchmark/verilog/operators/eightbit_arithmetic_power.v:15.12-15.22.",
2569-
"wire '\\c' is assigned in a block at regression_test/benchmark/verilog/operators/eightbit_arithmetic_power.v:16.18-16.23.",
2570-
"Ignoring module eightbit_arithmetic_power because it contains processes (run 'proc' command first).",
2571-
"Ignoring module eightbit_arithmetic_power because it contains processes (run 'proc' command first).",
2572-
"Ignoring module eightbit_arithmetic_power because it contains processes (run 'proc' command first)."
2573-
],
2574-
"max_rss(MiB)": 24.8,
2575-
"exec_time(ms)": 38.3,
2576-
"elaboration_time(ms)": 0.9,
2577-
"optimization_time(ms)": 0,
2578-
"techmap_time(ms)": 0.1,
2579-
"synthesis_time(ms)": 2.5,
2580-
"Pi": 10,
2581-
"Po": 8,
2582-
"logic element": 2,
2583-
"generic logic size": 6,
2584-
"Longest Path": 4,
2585-
"Average Path": 4,
2586-
"Estimated LUTs": 6,
2587-
"Total Node": 2,
2588-
"Wires": 34,
2589-
"Wire Bits": 34,
2590-
"Public Wires": 18,
2591-
"Public Wire Bits": 18,
2592-
"Total Cells": 17,
2593-
"MUX": 8,
2594-
"DFFs": [
2595-
"$_DFF_P_ 8"
2596-
],
2597-
"pow": 1
2598-
},
2599-
"operators/eightbit_arithmetic_power/no_arch": {
2600-
"test_name": "operators/eightbit_arithmetic_power/no_arch",
2601-
"warnings": [
2602-
"wire '\\c' is assigned in a block at regression_test/benchmark/verilog/operators/eightbit_arithmetic_power.v:15.12-15.22.",
2603-
"wire '\\c' is assigned in a block at regression_test/benchmark/verilog/operators/eightbit_arithmetic_power.v:16.18-16.23.",
2604-
"Ignoring module eightbit_arithmetic_power because it contains processes (run 'proc' command first).",
2605-
"Ignoring module eightbit_arithmetic_power because it contains processes (run 'proc' command first).",
2606-
"Ignoring module eightbit_arithmetic_power because it contains processes (run 'proc' command first)."
2607-
],
2608-
"max_rss(MiB)": 12.8,
2609-
"exec_time(ms)": 5.7,
2610-
"elaboration_time(ms)": 0.7,
2611-
"optimization_time(ms)": 0,
2612-
"techmap_time(ms)": 0.4,
2613-
"synthesis_time(ms)": 4.4,
2614-
"Pi": 10,
2615-
"Po": 8,
2616-
"logic element": 2,
2617-
"Longest Path": 4,
2618-
"Average Path": 4,
2619-
"Estimated LUTs": 2,
2620-
"Total Node": 2,
2621-
"Wires": 34,
2622-
"Wire Bits": 34,
2623-
"Public Wires": 18,
2624-
"Public Wire Bits": 18,
2625-
"Total Cells": 17,
2626-
"MUX": 8,
2627-
"DFFs": [
2628-
"$_DFF_P_ 8"
2629-
],
2630-
"pow": 1
2631-
},
26322494
"operators/macromudule_test/k6_frac_N10_frac_chain_mem32K_40nm": {
26332495
"test_name": "operators/macromudule_test/k6_frac_N10_frac_chain_mem32K_40nm",
26342496
"exit": 1,
@@ -4222,120 +4084,6 @@
42224084
"$_DFF_P_ 3"
42234085
]
42244086
},
4225-
"operators/twobits_arithmetic_power/k6_frac_N10_frac_chain_mem32K_40nm": {
4226-
"test_name": "operators/twobits_arithmetic_power/k6_frac_N10_frac_chain_mem32K_40nm",
4227-
"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
4228-
"warnings": [
4229-
"wire '\\out' is assigned in a block at regression_test/benchmark/verilog/operators/twobits_arithmetic_power.v:22.25-22.38.",
4230-
"wire '\\out' is assigned in a block at regression_test/benchmark/verilog/operators/twobits_arithmetic_power.v:23.25-23.36.",
4231-
"Ignoring module simple_op because it contains processes (run 'proc' command first).",
4232-
"Ignoring module simple_op because it contains processes (run 'proc' command first).",
4233-
"Ignoring module simple_op because it contains processes (run 'proc' command first)."
4234-
],
4235-
"Pi": 6,
4236-
"Po": 5,
4237-
"logic element": 2,
4238-
"generic logic size": 4,
4239-
"Longest Path": 4,
4240-
"Average Path": 3,
4241-
"Estimated LUTs": 4,
4242-
"Total Node": 2,
4243-
"Wires": 19,
4244-
"Wire Bits": 19,
4245-
"Public Wires": 11,
4246-
"Public Wire Bits": 11,
4247-
"Total Cells": 9,
4248-
"MUX": 4,
4249-
"DFFs": [
4250-
"$_DFF_P_ 4"
4251-
],
4252-
"pow": 1
4253-
},
4254-
"operators/twobits_arithmetic_power/k6_N10_40nm": {
4255-
"test_name": "operators/twobits_arithmetic_power/k6_N10_40nm",
4256-
"architecture": "k6_N10_40nm.xml",
4257-
"warnings": [
4258-
"wire '\\out' is assigned in a block at regression_test/benchmark/verilog/operators/twobits_arithmetic_power.v:22.25-22.38.",
4259-
"wire '\\out' is assigned in a block at regression_test/benchmark/verilog/operators/twobits_arithmetic_power.v:23.25-23.36.",
4260-
"Ignoring module simple_op because it contains processes (run 'proc' command first).",
4261-
"Ignoring module simple_op because it contains processes (run 'proc' command first).",
4262-
"Ignoring module simple_op because it contains processes (run 'proc' command first)."
4263-
],
4264-
"Pi": 6,
4265-
"Po": 5,
4266-
"logic element": 2,
4267-
"generic logic size": 6,
4268-
"Longest Path": 4,
4269-
"Average Path": 3,
4270-
"Estimated LUTs": 2,
4271-
"Total Node": 2,
4272-
"Wires": 19,
4273-
"Wire Bits": 19,
4274-
"Public Wires": 11,
4275-
"Public Wire Bits": 11,
4276-
"Total Cells": 9,
4277-
"MUX": 4,
4278-
"DFFs": [
4279-
"$_DFF_P_ 4"
4280-
],
4281-
"pow": 1
4282-
},
4283-
"operators/twobits_arithmetic_power/k6_N10_mem32K_40nm": {
4284-
"test_name": "operators/twobits_arithmetic_power/k6_N10_mem32K_40nm",
4285-
"architecture": "k6_N10_mem32K_40nm.xml",
4286-
"warnings": [
4287-
"wire '\\out' is assigned in a block at regression_test/benchmark/verilog/operators/twobits_arithmetic_power.v:22.25-22.38.",
4288-
"wire '\\out' is assigned in a block at regression_test/benchmark/verilog/operators/twobits_arithmetic_power.v:23.25-23.36.",
4289-
"Ignoring module simple_op because it contains processes (run 'proc' command first).",
4290-
"Ignoring module simple_op because it contains processes (run 'proc' command first).",
4291-
"Ignoring module simple_op because it contains processes (run 'proc' command first)."
4292-
],
4293-
"Pi": 6,
4294-
"Po": 5,
4295-
"logic element": 2,
4296-
"generic logic size": 6,
4297-
"Longest Path": 4,
4298-
"Average Path": 3,
4299-
"Estimated LUTs": 2,
4300-
"Total Node": 2,
4301-
"Wires": 19,
4302-
"Wire Bits": 19,
4303-
"Public Wires": 11,
4304-
"Public Wire Bits": 11,
4305-
"Total Cells": 9,
4306-
"MUX": 4,
4307-
"DFFs": [
4308-
"$_DFF_P_ 4"
4309-
],
4310-
"pow": 1
4311-
},
4312-
"operators/twobits_arithmetic_power/no_arch": {
4313-
"test_name": "operators/twobits_arithmetic_power/no_arch",
4314-
"warnings": [
4315-
"wire '\\out' is assigned in a block at regression_test/benchmark/verilog/operators/twobits_arithmetic_power.v:22.25-22.38.",
4316-
"wire '\\out' is assigned in a block at regression_test/benchmark/verilog/operators/twobits_arithmetic_power.v:23.25-23.36.",
4317-
"Ignoring module simple_op because it contains processes (run 'proc' command first).",
4318-
"Ignoring module simple_op because it contains processes (run 'proc' command first).",
4319-
"Ignoring module simple_op because it contains processes (run 'proc' command first)."
4320-
],
4321-
"Pi": 6,
4322-
"Po": 5,
4323-
"logic element": 2,
4324-
"Longest Path": 4,
4325-
"Average Path": 3,
4326-
"Estimated LUTs": 2,
4327-
"Total Node": 2,
4328-
"Wires": 19,
4329-
"Wire Bits": 19,
4330-
"Public Wires": 11,
4331-
"Public Wire Bits": 11,
4332-
"Total Cells": 9,
4333-
"MUX": 4,
4334-
"DFFs": [
4335-
"$_DFF_P_ 4"
4336-
],
4337-
"pow": 1
4338-
},
43394087
"operators/twobits_logical_greater_equal_than/k6_frac_N10_frac_chain_mem32K_40nm": {
43404088
"test_name": "operators/twobits_logical_greater_equal_than/k6_frac_N10_frac_chain_mem32K_40nm",
43414089
"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",

parmys/regression_test/benchmark/verilog/operators/eightbit_arithmetic_power.v renamed to parmys/regression_test/benchmark/verilog/operators/eightbit_arithmetic_power.v.skip

File renamed without changes.

parmys/regression_test/benchmark/verilog/operators/twobits_arithmetic_power.v renamed to parmys/regression_test/benchmark/verilog/operators/twobits_arithmetic_power.v.skip

File renamed without changes.

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