parmys doc update

Author: poname

doc/src/odin/index.rst

@@ -6,6 +6,11 @@ Odin II
 
 Odin II is used for logic synthesis and elaboration, converting a subset of the Verilog Hardware Description Language (HDL) into a BLIF netlist.
 
+.. note::
+    Odin-II has been deprecated and will be removed in a future version. Now VTR uses Parmys as the default frontend which utilizes Yosys as elaborator with partial mapping features enabled.
+
+    To build the VTR flow with the Odin-II front-end you may use the VTR Makefile wrapper, by calling the ``make CMAKE_PARAMS="-DWITH_ODIN=ON"`` command in the `$VTR_ROOT` directory.
+
 .. toctree::
    :glob:
    :maxdepth: 2

doc/src/parmys/parmys_plugin.rst

@@ -6,7 +6,7 @@ Parmys Plugin
 Parmys (Partial Mapper for Yosys) is a Yosys plugin that performs intelligent partial mapping (inference, binding, and hard/soft logic trade-offs) from Odin-II.
 Please see `Parmys-Plugin GitHub <https://github.com/CAS-Atlantic/parmys-plugin.git>`_ repository for more information.
 
-Available parameters are:
+Available parameters
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 .. option:: -a ARCHITECTURE_FILE

doc/src/vtr/run_vtr_flow.rst

@@ -63,10 +63,10 @@ They will cause VPR to perform only :ref:`packing and placement <general_options
 .. code-block:: bash
 
     # Using the Yosys conventional Verilog parser
-    ./run_vtr_flow <path/to/Verilog/File> <path/to/arch/file> -start yosys
+    ./run_vtr_flow <path/to/Verilog/File> <path/to/arch/file>
 
     # Using the Yosys-SystemVerilog plugin if installed, otherwise the Yosys conventional Verilog parser
-    ./run_vtr_flow <path/to/SystemVerilog/File> <path/to/arch/file> -start yosys
+    ./run_vtr_flow <path/to/SystemVerilog/File> <path/to/arch/file> -parser system-verilog
 
 Running the VTR flow with the default configuration using the Yosys standalone front-end.
 The parser for these runs is considered the Yosys conventional Verilog/SystemVerilog parser (i.e., ``read_verilog -sv``), as the parser is not explicitly specified.
@@ -77,7 +77,7 @@ The parser for these runs is considered the Yosys conventional Verilog/SystemVer
     ./run_vtr_flow <path/to/SystemVerilog/File> <path/to/arch/file> -parser system-verilog
 
     # Using the Surelog plugin if installed, otherwise failure on the unsupported file type
-    ./run_vtr_flow <path/to/UHDM/File> <path/to/arch/file> -start yosys -parser surelog
+    ./run_vtr_flow <path/to/UHDM/File> <path/to/arch/file> -parser surelog
 
 Running the default VTR flow using the Parmys standalone front-end.
 The Yosys HDL parser is considered as Yosys-SystemVerilog plugin (i.e., ``read_systemverilog``) and Yosys UHDM plugin (i.e., ``read_uhdm``), respectively.
@@ -86,7 +86,7 @@ Utilizing Yosys plugins requires passing the ``-DYOSYS_SV_UHDM_PLUGIN=ON`` compi
 .. code-block:: bash
 
     # Using the Parmys (Partial Mapper for Yosys) plugin as partial mapper
-    ./run_vtr_flow <path/to/Verilog/File> <path/to/arch/file> -start yosys
+    ./run_vtr_flow <path/to/Verilog/File> <path/to/arch/file>
 
 Will run the VTR flow (default configuration) with Yosys frontend using Parmys plugin as partial mapper. To utilize the Parmys plugin, the ``-DYOSYS_PARMYS_PLUGIN=ON`` compile flag should be passed while building the VTR project with Yosys as a frontend.
 

vtr_flow/scripts/python_libs/vtr/parmys/parmys.py

@@ -1,5 +1,5 @@
 """
-    Module to run YOSYS with its various arguments
+    Module to run Parmys with its various arguments
 """
 import os
 import shutil
@@ -82,11 +82,11 @@ def init_config_file(
     min_hard_mult_size,
     min_hard_adder_size,
 ):
-    """initializing the raw odin config file"""
+    """initializing the raw xml config file"""
     # specify the input files type
     file_extension = os.path.splitext(circuit_list[0])[-1]
     if file_extension not in FILE_TYPES:
-        raise vtr.VtrError("Inavlid input file type '{}'".format(file_extension))
+        raise vtr.VtrError("Invalid input file type '{}'".format(file_extension))
     input_file_type = FILE_TYPES[file_extension]
 
     # Update the config file
@@ -135,7 +135,7 @@ def run(
     min_hard_adder_size=1,
 ):
     """
-    Runs YOSYS on the specified architecture file and circuit file
+    Runs Yosys on the specified architecture file and circuit
 
     .. note :: Usage: vtr.parmys.run(<architecture_file>,<circuit_file>,<output_netlist>,[OPTIONS])
 
@@ -162,16 +162,16 @@ def run(
             Directory to run in (created if non-existent)
 
         parmys_args:
-            A dictionary of keyword arguments to pass on to PARMYS
+            A dictionary of keyword arguments to pass on to Parmys
 
         log_filename :
             File to log result to
 
         yosys_exec:
-            YOSYS executable to be run
+            Yosys executable to be run
 
         yosys_script:
-            The YOSYS script file
+            The Yosys script file
 
     """
     temp_dir = Path(temp_dir) if not isinstance(temp_dir, Path) else temp_dir