FlatRecon: Use blif file for the basic odin test

Author: haydar-c

vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_flat_recon/config/config.txt

@@ -3,7 +3,7 @@
 ##############################################
 
 # Path to directory of circuits to use
-circuits_dir=benchmarks/verilog
+circuits_dir=tasks/regression_tests/vtr_reg_basic_odin/basic_flat_recon/constraints
 
 # Path to directory of architectures to use
 archs_dir=arch/timing
@@ -12,17 +12,17 @@ archs_dir=arch/timing
 arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
 
 # Add circuits to list to sweep
-circuit_list_add=spree.v
+circuit_list_add=spree.blif
 
 # Constrain the circuits to their devices
-circuit_constraint_list_add=(spree.v,            device=vtr_extra_small)
+circuit_constraint_list_add=(spree.blif,            device=vtr_extra_small)
 
 # Constrain the circuits to their channel widths
 #       1.3 * minW
-circuit_constraint_list_add=(spree.v,            route_chan_width=78)
+circuit_constraint_list_add=(spree.blif,            route_chan_width=78)
 
 # Reaf flat placement constraints
-circuit_constraint_list_add=(spree.v,    read_flat_place=../../../../../basic_flat_recon/constraints/spree.fplace)
+circuit_constraint_list_add=(spree.blif,    read_flat_place=../../../../../basic_flat_recon/constraints/spree.fplace)
 
 # Parse info and how to parse
 parse_file=vpr_ap_reconstruction.txt
@@ -34,5 +34,5 @@ qor_parse_file=qor_ap_flatrecon_fl_fixed_chan_width.txt
 pass_requirements_file=pass_requirements_ap_reconstruction.txt
 
 # Pass the script params while writing the vpr constraints.
-#       With AP
-script_params=-track_memory_usage --timing_analysis off --analytical_place --ap_detailed_placer none  --ap_full_legalizer flat-recon -start odin
+# Starting from vpr since we want to test on the same blif file. The flat placement file will share same atom names here.
+script_params=-track_memory_usage --timing_analysis off --analytical_place --ap_detailed_placer none  --ap_full_legalizer flat-recon -starting_stage vpr

vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_flat_recon/config/golden_results.txt

@@ -1,2 +1,2 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	post_fl_atom_err	post_fl_total_disp	post_fl_avg_disp	post_fl_max_disp	ap_fl_max_rss	num_total_clusters	
-k6_frac_N10_frac_chain_mem32K_40nm.xml	spree.v	common	3.25	vpr	89.11 MiB		-1	-1	1.35	40000	16	0.41	-1	-1	39028	-1	-1	61	45	3	1	success	v8.0.0-13697-g4ea6b570aa-dirty	release IPO VTR_ASSERT_LEVEL=1 gprof	GNU 11.4.0 on Linux-6.8.0-52-generic x86_64	2025-08-25T20:29:05	haydar-Precision-5820-Tower	/home/haydar/vtr-verilog-to-routing/vtr_flow/tasks	91244	45	32	944	0	1	800	142	20	20	400	-1	vtr_extra_small	-1	-1	-1	-1	-1	-1	-1	-1	89.1 MiB	0.85	-1	-1	-1	-1	-1	-1	0.07	-1	-1	-1	-1	89.1 MiB	0.85	89.1 MiB	0.75	-1	-1	-1	-1	-1	-1	-1	-1	0.00457586	0.0039846	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0.000000	0.000000	0.000000	0.000000	89.1	142	
+k6_frac_N10_frac_chain_mem32K_40nm.xml	spree.blif	common	1.09	vpr	84.61 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	61	45	3	1	success	v8.0.0-13835-g615520f537	Release VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.8.0-65-generic x86_64	2025-08-27T08:45:05	haydar-Precision-5820-Tower	/home/haydar/vtr-verilog-to-routing/vtr_flow/tasks	86636	45	32	944	0	1	800	142	20	20	400	-1	vtr_extra_small	-1	-1	-1	-1	-1	-1	-1	-1	84.6 MiB	0.72	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	84.6 MiB	0.72	84.6 MiB	0.71	-1	-1	-1	-1	-1	-1	-1	-1	0	0	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0.000000	0.000000	0.000000	0.000000	84.6	142