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lines changed Original file line number Diff line number Diff line change 1+ <traffic_flows>
2+
3+ <single_flow src=".*noc_router_adapter_block_one.*" dst=".*noc_router_adapter_block_two.*" bandwidth="4e5" latency_cons="3e-9" />
4+
5+ </traffic_flows>
Original file line number Diff line number Diff line change 1+ ##############################################
2+ # Configuration file for running experiments
3+ ##############################################
4+
5+ # Path to directory of circuits to use
6+ circuits_dir=benchmarks/noc/Synthetic_Designs/complex_2_noc_1D_chain
7+
8+ # Path to directory of architectures to use
9+ archs_dir=arch/noc/mesh_noc_topology
10+
11+ # Add circuits to list to sweep
12+ circuit_list_add=complex_2_noc_1D_chain.blif
13+
14+ # Add architectures to list to sweep
15+ arch_list_add=stratixiv_arch.timing_with_a_embedded_3X3_mesh_noc_topology_2.xml
16+
17+ # Parse info and how to parse
18+ parse_file=vpr_noc.txt
19+
20+ # How to parse QoR info
21+ qor_parse_file=qor_noc_spec.txt
22+
23+ # Pass requirements
24+ #SARA_TODO: should add this later on, after making sure it is working
25+ pass_requirements_file=pass_requirements.txt
26+
27+ # Script parameters
28+ script_params =-starting_stage vpr --noc on --noc_flows_file ../../../../complex_2_noc_1D_chain.flows --noc_routing_algorithm xy_routing --device "EP4SGX110"
Original file line number Diff line number Diff line change 1+ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency
2+ stratixiv_arch.timing_with_a_embedded_3X3_mesh_noc_topology_2.xml complex_2_noc_1D_chain.blif common 619.37 vpr 1.80 GiB -1 2 -1 -1 success v8.0.0-6827-g874e0cb8d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2023-01-19T13:42:08 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/add_noc_testcases/vtr-verilog-to-routing/vtr_flow/tasks 1882820 2 32 2204 1661 1 1141 103 82 66 5412 -1 EP4SGX110 912.4 MiB 2.18 7959 1838.7 MiB 0.32 0.00 6.65955 -4642.85 -6.65955 6.65955 225.52 0.00198776 0.00164918 0.141682 0.118101 150 10479 36 0 0 5.26448e+07 9727.43 288.74 1.58054 1.37992 9961 29 3424 6115 3360378 496031 7.28264 7.28264 -5679.8 -7.28264 0 0 6.74649e+07 12465.8 41.46 0.81 0.231398 0.209765 400000 3e-09
Original file line number Diff line number Diff line change @@ -82,3 +82,4 @@ regression_tests/vtr_reg_strong/koios
8282regression_tests/vtr_reg_strong/koios_no_complex_dsp
8383regression_tests/vtr_reg_strong/strong_timing_fail
8484regression_tests/vtr_reg_strong/strong_timing_no_fail
85+ regression_tests/vtr_reg_strong/strong_noc
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