update timing no fail

Author: jmah76

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt

@@ -1,2 +1,2 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	yosys_synth_time	max_yosys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_time	placed_wirelength_est	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-k6_frac_N10_mem32K_40nm.xml	ch_intrinsics.v	common_-sdc_file_sdc/samples/easy_pass_timing.sdc	38.93	vpr	560.26 MiB		0.30	119016	-1	-1	3	0.26	-1	-1	38188	-1	-1	65	99	1	0	success	v8.0.0-5549-gc7bbbb9fa	release IPO VTR_ASSERT_LEVEL=2 sanitizers	GNU 9.4.0 on Linux-5.13.0-28-generic x86_64	2022-07-01T09:16:33	betzgrp-pchenry	/home/mahjenni/Desktop/vtr-verilog-to-routing	573704	99	130	363	493	1	252	295	12	12	144	clb	auto	3.57	-1	0.27	0.08	nan	0	0	nan	3.78	0.00339061	0.0030254	0.0189794	0.0171543	38	1996	7	5.66058e+06	4.05111e+06	319130.	2216.18	14.65	1.0871	0.996048	1893	9	431	533	46037	12837	nan	nan	0	0	0	0	406292.	2821.48	0.72	0.33	0.0984812	0.0909516	
+k6_frac_N10_mem32K_40nm.xml	ch_intrinsics.v	common_-sdc_file_sdc/samples/easy_pass_timing.sdc	2.58	abc	36.98 MiB		0.09	9620	-1	-1	3	0.26	-1	-1	37872	-1	-1	65	99	1	0	success	v8.0.0-5551-g0e9f0fef7	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-5.13.0-28-generic x86_64	2022-07-01T13:02:30	betzgrp-pchenry	/home/mahjenni/Desktop/vtr-verilog-to-routing	31756	99	130	363	493	1	252	295	12	12	144	clb	auto	0.13	-1	0.01	0.00	nan	0	0	nan	0.22	0.000301481	0.000272794	0.00222634	0.00210433	38	1996	7	5.66058e+06	4.05111e+06	319130.	2216.18	0.43	0.0652805	0.060038	1893	9	431	533	46037	12837	nan	nan	0	0	0	0	406292.	2821.48	0.09	0.02	0.0105097	0.00996907