added correct chanel distribution and made sure golden was up to date

Author: WhiteNinjaZ

vtr_flow/arch/xilinx/simple-7series.xml

@@ -74,7 +74,7 @@
     <!-- TODO: PR #1883 allows for different horizontal and vertical uniform channel widths (an attribute of Xilinx arches)
     until that PR is merged, we give equal distributions here. -->
     <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
+      <x distr="uniform" peak="0.652632"/>
       <y distr="uniform" peak="1.000000"/>
     </chan_width_distr>
     <switch_block type="wilton" fs="3"/>

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_support/config/config.txt

@@ -15,7 +15,6 @@ circuit_list_add=stereovision3.v
 # Add architectures to list to sweep
 arch_list_add=simple-7series.xml
 
-############################ The following configurations are not changed and have been checked #####################
 
 # Parse info and how to parse
 parse_file=vpr_standard.txt
@@ -26,4 +25,4 @@ qor_parse_file=qor_standard.txt
 # Pass requirements
 pass_requirements_file=pass_requirements.txt
 
-script_params=-track_memory_usage # TODO: Check this ##############################
+script_params=-track_memory_usage