easy timint pass sdc file fixed

Author: jmah76

vtr_flow/sdc/samples/easy_pass_timing.sdc

@@ -1,12 +1,4 @@
-create_clock -period 10000 -name easy 
+create_clock -period 10000 *
 
-set_input_delay -clock easy 0 [get_ports{*}] 
-
-set_output_delay -clock easy 0 [get_ports{*}]
-
-set_min_delay 0 -from [get_clocks{*}] -to [get_clocks{*}]
-
-set_max_delay 0 -from [get_clocks{*}] -to [get_clocks{*}]
-
-set_false_path -from[get_clocks{*}] -to [get_clocks{*}]
+##set_false_path -from[get_clocks{*}] -to [get_clocks{*}]