koios reg test odin

Author: poname

odin_ii/regression_test/benchmark/suite/heavy_suite/task_list.conf

@@ -1,4 +1,3 @@
 regression_test/benchmark/task/full
 regression_test/benchmark/task/large
-regression_test/benchmark/task/koios
-
+regression_test/benchmark/suite/koios_weekly_suite

odin_ii/regression_test/benchmark/suite/koios_nightly_suite/task_list.conf

@@ -0,0 +1,2 @@
+regression_test/benchmark/task/koios/koios_medium
+regression_test/benchmark/task/koios/koios_medium_no_hb

odin_ii/regression_test/benchmark/suite/koios_weekly_suite/task_list.conf

@@ -0,0 +1,2 @@
+regression_test/benchmark/task/koios/koios_large
+regression_test/benchmark/task/koios/koios_large_no_hb

odin_ii/regression_test/benchmark/suite/light_suite/task_list.conf

@@ -9,4 +9,5 @@ regression_test/benchmark/task/syntax
 regression_test/benchmark/task/FIR
 regression_test/benchmark/task/micro
 regression_test/benchmark/suite/complex_synthesis_suite
-regression_test/benchmark/suite/vtr_multiclock_suite
+regression_test/benchmark/suite/vtr_multiclock_suite
+regression_test/benchmark/suite/koios_nightly_suite

odin_ii/regression_test/benchmark/task/koios/koios_large/synthesis_result.json

@@ -0,0 +1,45 @@
+########################
+# Koios benchmarks config
+########################
+
+regression_params=--disable_simulation --verbose
+script_synthesis_params=--limit_ressource --time_limit 14400s
+script_simulation_params=--limit_ressource --time_limit 14400s
+
+#-------------------------------------------------------
+# specify the directory to look for architecture file in
+#-------------------------------------------------------
+archs_dir=../vtr_flow/arch/COFFE_22nm
+
+#-------------------------------------------------------
+# specify the architecture file
+#-------------------------------------------------------
+arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml
+
+#-------------------------------------------------------
+# specify the directory to look for benchmarks in
+#-------------------------------------------------------
+circuits_dir=regression_test/benchmark/verilog/koios_dummy
+
+#-------------------------------------------------------
+# specify the benchmarks
+#-------------------------------------------------------
+circuit_list_add=lenet.v
+circuit_list_add=clstm_like.small.v
+circuit_list_add=clstm_like.medium.v
+circuit_list_add=clstm_like.large.v
+circuit_list_add=lstm.v
+circuit_list_add=gemm_layer.v
+circuit_list_add=tpu_like.large.os.v
+circuit_list_add=tpu_like.large.ws.v
+circuit_list_add=tdarknet_like.small.v
+circuit_list_add=tdarknet_like.large.v
+circuit_list_add=dla_like.medium.v
+
+#-------------------------------------------------------
+# Some benchmarks instantiate hard dsp and memory blocks 
+# This functionality is guarded under the `complex_dsp` and `hard_mem` macros. 
+# The dummy verilog file 
+# defines this macros, thereby enabling instantiations of the hard blocks
+
+synthesis_parse_file=regression_test/parse_result/conf/synth.toml

odin_ii/regression_test/benchmark/task/koios/koios_large/task.conf

@@ -0,0 +1,39 @@
+########################
+# Koios benchmarks config
+########################
+
+regression_params=--disable_simulation --verbose
+script_synthesis_params=--limit_ressource --time_limit 14400s
+script_simulation_params=--limit_ressource --time_limit 14400s
+
+#-------------------------------------------------------
+# specify the directory to look for architecture file in
+#-------------------------------------------------------
+archs_dir=../vtr_flow/arch/COFFE_22nm
+
+#-------------------------------------------------------
+# specify the architecture file
+#-------------------------------------------------------
+arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml
+
+#-------------------------------------------------------
+# specify the directory to look for benchmarks in
+#-------------------------------------------------------
+circuits_dir=../vtr_flow/benchmarks/verilog/koios
+
+#-------------------------------------------------------
+# specify the benchmarks
+#-------------------------------------------------------
+circuit_list_add=lenet.v
+circuit_list_add=clstm_like.small.v
+circuit_list_add=clstm_like.medium.v
+circuit_list_add=clstm_like.large.v
+circuit_list_add=lstm.v
+circuit_list_add=gemm_layer.v
+circuit_list_add=tpu_like.large.os.v
+circuit_list_add=tpu_like.large.ws.v
+circuit_list_add=tdarknet_like.small.v
+circuit_list_add=tdarknet_like.large.v
+circuit_list_add=dla_like.medium.v
+
+synthesis_parse_file=regression_test/parse_result/conf/synth.toml

odin_ii/regression_test/benchmark/task/koios/koios_large_no_hb/synthesis_result.json

@@ -2,7 +2,7 @@
 # Koios benchmarks config
 ########################
 
-regression_params=--disable_simulation --disable_parallel_jobs --verbose
+regression_params=--disable_simulation --verbose
 script_synthesis_params=--limit_ressource --time_limit 14400s
 script_simulation_params=--limit_ressource --time_limit 14400s
 
@@ -19,7 +19,7 @@ arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml
 #-------------------------------------------------------
 # specify the directory to look for benchmarks in
 #-------------------------------------------------------
-circuits_dir=../../../../vtr_flow/benchmarks/verilog/koios
+circuits_dir=regression_test/benchmark/verilog/koios_dummy
 
 #-------------------------------------------------------
 # specify the benchmarks
@@ -31,25 +31,16 @@ circuit_list_add=bnn.v
 circuit_list_add=attention_layer.v
 circuit_list_add=conv_layer_hls.v
 circuit_list_add=conv_layer.v
-circuit_list_add=gemm_layer.v
 circuit_list_add=eltwise_layer.v
 circuit_list_add=robot_rl.v
 circuit_list_add=reduction_layer.v
 circuit_list_add=spmv.v
 circuit_list_add=softmax.v
 
-#-------------------------------------------------------
-# specify the directory to look for include file in
-#-------------------------------------------------------
-includes_dir=../../../../vtr_flow/benchmarks/verilog/koios
-
-#-------------------------------------------------------
-# specify the include files
 #-------------------------------------------------------
 # Some benchmarks instantiate hard dsp and memory blocks 
 # This functionality is guarded under the `complex_dsp` and `hard_mem` macros. 
-# The hard_block_include.v file 
+# The dummy verilog file 
 # defines this macros, thereby enabling instantiations of the hard blocks
-include_list_add=hard_block_include.v
 
 synthesis_parse_file=regression_test/parse_result/conf/synth.toml