speed up sv

Author: poname

parmys/regression_test/benchmark/suite/koios_weekly_suite/task_list.conf

@@ -2,5 +2,5 @@ regression_test/benchmark/task/koios/large
 regression_test/benchmark/task/koios/large_no_hb
 regression_test/benchmark/task/koios/proxy
 regression_test/benchmark/task/koios/proxy_no_hb
-#regression_test/benchmark/task/koios/sv
-#regression_test/benchmark/task/koios/sv_no_hb
+regression_test/benchmark/task/koios/sv
+regression_test/benchmark/task/koios/sv_no_hb

parmys/regression_test/benchmark/task/koios/sv/task.conf

@@ -2,7 +2,7 @@
 # Koios benchmarks config
 ########################
 
-regression_params=--disable_simulation --disable_parallel_jobs --verbose
+regression_params=--disable_simulation --verbose
 script_synthesis_params=--limit_ressource --time_limit 14400s
 script_simulation_params=--limit_ressource --time_limit 14400s
 

parmys/regression_test/benchmark/task/koios/sv_no_hb/task.conf

@@ -2,7 +2,7 @@
 # Koios benchmarks config
 ########################
 
-regression_params=--disable_simulation --disable_parallel_jobs --verbose
+regression_params=--disable_simulation --verbose
 script_synthesis_params=--limit_ressource --time_limit 14400s
 script_simulation_params=--limit_ressource --time_limit 14400s
 

parmys/regression_test/benchmark/task/operators/task.conf

@@ -15,7 +15,7 @@ arch_list_add=k6_N10_mem32K_40nm.xml
 arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
 
 # setup the circuits
-circuits_dir=regression_test/benchmark/verilog/
+circuits_dir=regression_test/benchmark/verilog
 
 circuit_list_add=operators/*.v
 

parmys/regression_test/benchmark/task/vtr/task.conf

@@ -1,7 +1,7 @@
 ########################
 # verilog benchmarks config
 ########################
-regression_params=--disable_simulation --disable_parallel_jobs --verbose
+regression_params=--disable_simulation --verbose
 
 script_synthesis_params=--time_limit 14400s
 script_simulation_params=--time_limit 14400s

vtr_flow/misc/yosys/synthesis.tcl

@@ -9,24 +9,24 @@ setattr -mod -set keep_hierarchy 1 dual_port_ram
 
 puts "Using parmys as partial mapper"
 
-# QQQ arch file
-# XXX input files
-# YYY other args
-# CCC config file
-# ZZZ output file
+# arch file: QQQ
+# input files: [XXX]
+# other args: [YYY]
+# config file: CCC
+# output file: ZZZ
 
 parmys_arch -a QQQ
 
 if {$env(PARSER) == "surelog" } {
 	puts "Using Yosys read_uhdm command"
 	plugin -i systemverilog
 	yosys -import
-	read_uhdm -debug XXX
+	read_uhdm XXX
 } elseif {$env(PARSER) == "system-verilog" } {
 	puts "Using Yosys read_systemverilog command"
 	plugin -i systemverilog
 	yosys -import
-	read_systemverilog -debug XXX
+	read_systemverilog XXX
 } elseif {$env(PARSER) == "default" } {
 	puts "Using Yosys read_verilog command"
 	read_verilog -sv -nolatches XXX