Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into pres_fac_max

Author: amin1377

.github/scripts/install_dependencies.sh

@@ -29,6 +29,7 @@ sudo apt install -y \
   libncurses5-dev \
   libx11-dev \
   libxft-dev \
+  libxml2-utils \
   libxml++2.6-dev \
   libreadline-dev \
   tcllib \

CMakeLists.txt

@@ -418,11 +418,13 @@ if(${WITH_PARMYS}) # define cmake params to compile Yosys
         set(MAKE_PROGRAM "make")
     endif()
 
-    if(NOT DEFINED "${CMAKE_BUILD_PARALLEL_LEVEL}")
-        set(CUSTOM_BUILD_PARALLEL_LEVEL 16)
-    else()
-        set(CUSTOM_BUILD_PARALLEL_LEVEL "${CMAKE_BUILD_PARALLEL_LEVEL}")
-    endif()
+    # Commented out since a make file should not call another make command with
+    # threads. It should pass this information from the parent automatically.
+    # if(NOT DEFINED "${CMAKE_BUILD_PARALLEL_LEVEL}")
+    #     set(CUSTOM_BUILD_PARALLEL_LEVEL 16)
+    # else()
+    #     set(CUSTOM_BUILD_PARALLEL_LEVEL "${CMAKE_BUILD_PARALLEL_LEVEL}")
+    # endif()
     add_subdirectory(yosys)
 endif()
 

blifexplorer/CMakeLists.txt

@@ -2,7 +2,7 @@ cmake_minimum_required(VERSION 3.16)
 
 project("blifexplorer")
 
-set(CMAKE_CXX_STANDARD 14)
+set(CMAKE_CXX_STANDARD 17)
 set(CMAKE_CXX_STANDARD_REQUIRED ON)
 set(CMAKE_CXX_EXTENSIONS OFF)
 

doc/src/quickstart/index.rst

@@ -48,6 +48,12 @@ On most unix-like systems you can run:
 
     > make
 
+The default front-end for VTR is :ref:`Parmys<parmys>`, but you can build with ODIN II instead using the command below. This is required to run :ref:`Synthesizing with ODIN II<synthesizing_with_odin_ii>`.
+
+.. code-block:: bash
+
+    > make CMAKE_PARAMS="-DWITH_ODIN=on"
+
 from the VTR root directory (hereafter referred to as :term:`$VTR_ROOT`) to build VTR.
 
 .. note:: 
@@ -63,6 +69,8 @@ from the VTR root directory (hereafter referred to as :term:`$VTR_ROOT`) to buil
     * define VTR_ROOT as a variable in your shell (e.g. if ``~/trees/vtr`` is the path to the VTR source tree on your machine, run the equivalent of ``VTR_ROOT=~/trees/vtr`` in BASH) which will allow you to run the commands as written in this guide, or
     * manually replace `$VTR_ROOT` in the example commands below with your path to the VTR source tree.
 
+
+
 For more details on building VTR on various operating systems/platforms see :doc:`Building VTR</BUILDING>`.
 
 
@@ -235,6 +243,7 @@ Next we need to run the three main sets of tools:
 * :ref:`ABC` performs 'logic optimization' which simplifies the circuit logic, and 'technology mapping' which converts logic equations into the Look-Up-Tables (LUTs) available on an FPGA, and
 * :ref:`VPR` which performs packing, placement and routing of the circuit to implement it on the targetted FPGA architecture.
 
+.. _synthesizing_with_odin_ii:
 Synthesizing with ODIN II
 ~~~~~~~~~~~~~~~~~~~~~~~~~
 

doc/src/tutorials/flow/basic_flow.rst

@@ -17,16 +17,9 @@ The following steps show you to run the VTR design flow to map a sample circuit
 
         $VTR_ROOT/vtr_flow/scripts/run_vtr_task.py basic_no_timing 
         
-    The subdirectory ``regression_tests/vtr_reg_basic`` contains tests that are to be run before each commit. They check for basic functionallity to make sure nothing was           extremely out of order. This command runs the VTR flow on a set of circuits and a single architecture. 
+    The subdirectory ``regression_tests/vtr_reg_basic`` contains tests that are to be run before each commit. They check for basic functionality to make sure nothing was extremely out of order. This command runs the VTR flow on a set of circuits and a single architecture. 
     The files generated from the run are stored in ``basic_no_timing/run[#]`` where ``[#]`` is the number of runs you have done.
-    If this is your first time running the flow, the results will be stored in basic_no_timing/run001.
-    When the script completes, enter the following command:
-
-    .. code-block:: shell
-
-         ../../../scripts/python_libs/vtr/parse_vtr_task.py basic_no_timing/
-
-    This parses out the information of the VTR run and outputs the results in a text file called ``run[#]/parse_results.txt``.
+    If this is your first time running the flow, the results will be stored in basic_no_timing/run001. The command parses out the information of the VTR run and outputs the results in a text file called ``run[#]/parse_results.txt``.
 
     More info on how to run the flow on multiple circuits and architectures along with different options later.
     Before that, we need to ensure that the run that you have done works.

doc/src/vpr/basic_flow.rst

@@ -4,7 +4,7 @@ Basic flow
 The Place and Route process in VPR consists of several steps:
 
 - Packing (combinines primitives into complex blocks)
-- Placment (places complex blocks within the FPGA grid)
+- Placement (places complex blocks within the FPGA grid)
 - Routing (determines interconnections between blocks)
 - Analysis (analyzes the implementation)
 

doc/src/vpr/command_line_usage.rst

@@ -1304,6 +1304,14 @@ The following options are only valid when the router is in timing-driven mode (t
 
     **Default:** ``1.2``
 
+.. option:: --router_profiler_astar_fac <float>
+    
+    Controls the directedness of the timing-driven router's exploration when doing router delay profiling of an architecture.
+    The router delay profiling step is currently used to calculate the place delay matrix lookup.
+    Values between 1 and 2 are resonable; higher values trade some quality for reduced run-time.
+
+    **Default:** ``1.2``
+
 .. option:: --max_criticality <float>
 
     Sets the maximum fraction of routing cost that can come from delay (vs. coming from routability) for any net.

doc/src/vtr/benchmarks.rst

@@ -102,7 +102,7 @@ These designs use many precisions including binary, different fixed point types
     proxy               Proxy/synthetic benchmarks
     =================   ======================================
 
-The VTR benchmarks are provided as Verilog (enabling full flexibility to modify and change how the designs are implemented) under: ::
+The Koios benchmarks are provided as Verilog (enabling full flexibility to modify and change how the designs are implemented) under: ::
 
     $VTR_ROOT/vtr_flow/benchmarks/verilog/koios
 
@@ -207,4 +207,4 @@ real application domains. On the other hand, MLP benchmarks include modules that
 and move data. Pre-synthesized netlists for the synthetic benchmarks are added to VTR project, but MLP netlists should
 be downloaded separately.
 
-.. note:: The NoC MLP benchmarks are not included with the VTR release (due to their size). However they can be downloaded and extracted by running ``make get_noc_mlp_benchmarks`` from the root of the VTR tree.  They can also be `downloaded manually <https://www.eecg.utoronto.ca/~vaughn/titan/>`_.
+.. note:: The NoC MLP benchmarks are not included with the VTR release (due to their size). However they can be downloaded and extracted by running ``make get_noc_mlp_benchmarks`` from the root of the VTR tree.  They can also be `downloaded manually <https://www.eecg.utoronto.ca/~vaughn/titan/>`_.

libs/EXTERNAL/libcatch2

@@ -1,14 +1,16 @@
 #include "device_grid.h"
 
+#include <utility>
+
 DeviceGrid::DeviceGrid(std::string grid_name, vtr::NdMatrix<t_grid_tile, 3> grid)
-    : name_(grid_name)
-    , grid_(grid) {
+    : name_(std::move(grid_name))
+    , grid_(std::move(grid)) {
     count_instances();
 }
 
 DeviceGrid::DeviceGrid(std::string grid_name, vtr::NdMatrix<t_grid_tile, 3> grid, std::vector<t_logical_block_type_ptr> limiting_res)
-    : DeviceGrid(grid_name, grid) {
-    limiting_resources_ = limiting_res;
+    : DeviceGrid(std::move(grid_name), std::move(grid)) {
+    limiting_resources_ = std::move(limiting_res);
 }
 
 size_t DeviceGrid::num_instances(t_physical_tile_type_ptr type, int layer_num) const {