unused args removed

Author: poname

ODIN_II/SRC/odin_ii.cpp

@@ -460,16 +460,6 @@ void get_options(int argc, char** argv) {
         .nargs('+')
         .metavar("VERILOG_FILE");
 
-    input_grp.add_argument(global_args.input_files, "-s")
-        .help("List of SystemVerilog HDL file")
-        .nargs('+')
-        .metavar("SYSTEMVERILOG_FILE");
-
-    input_grp.add_argument(global_args.input_files, "-u")
-        .help("List of UHDM HDL file")
-        .nargs('+')
-        .metavar("UHDM_FILE");
-
     input_grp.add_argument(global_args.blif_file, "-b")
         .help("BLIF file")
         .metavar("BLIF_FILE");
@@ -663,9 +653,6 @@ void get_options(int argc, char** argv) {
                             a config file(-c)\n\t\
                             a BLIF file(-b)\n\t\
                             a Verilog file(-v)\n\t\
-                            a SystemVerilog file(-s)\n\t\
-                            an UHDM file(-u)\n\t\
-                            a TCL file including HDL designs(-S)\n\
                         Unless is used for infrastructure directly\n");
     }
 
@@ -683,10 +670,6 @@ void get_options(int argc, char** argv) {
         std::string arg_name = string_to_lower(global_args.input_files.argument_name());
         if (arg_name == "-v")
             configuration.input_file_type = file_type_e::VERILOG;
-        else if (arg_name == "-s")
-            configuration.input_file_type = file_type_e::SYSTEM_VERILOG;
-        else if (arg_name == "-u")
-            configuration.input_file_type = file_type_e::UHDM;
         else {
             // Unknown argument name, should have been already checked in the argparse library
             error_message(PARSE_ARGS, unknown_location,

doc/src/odin/dev_guide/testing.md

@@ -3,7 +3,7 @@
 The ``verify_odin.sh`` script will simulate the microbenchmarks and a larger set of benchmark circuits.
 These scripts use simulation results which have been verified against ModelSim.
 
-After you build Odin-II, run ``make test ELABORATOR=odin`` or ``make test`` to ensure that everything is working correctly on your system.
+After you build Odin-II, run ``make test`` to ensure that everything is working correctly on your system.
 The ``verify_odin.sh`` also simulates the blif output, as well as simulating the verilog with and without the
 architecture file.
 
@@ -32,4 +32,4 @@ You may now directly compare the vectors in the ``output_vectors`` file with tho
 > For simulation purposes, you may need to handle the ``GLOBAL_SIM_BASE_CLK`` signal in the ``input_vector`` by either adding this signal as an input signal to the top module or removing it from the ``input_vector`` file.
 
 To add the verified vectors and circuit to an existing test set, move the Verilog file (eg: ``test_circuit.v``) to the test set folder.
-Next, move the ``input_vectors`` file to the test set folder, and rename it ``test_circuit_$ELABORATOR_input`` (`$ELABORATOR: odin, yosys`). Finally, move the ``output_vectors`` file to the test set folder and rename it ``test_circuit_$ELABORATOR_output``.
+Next, move the ``input_vectors`` file to the test set folder, and rename it ``test_circuit_odin_input``. Finally, move the ``output_vectors`` file to the test set folder and rename it ``test_circuit_odin_output``.

doc/src/vtr/run_vtr_flow.rst

@@ -232,53 +232,10 @@ Detailed Command-line Options
 
     **Default:** 1
 
-.. option:: -elaborator <ELABORATOR>
-    
-    Specifies the elaborator of the synthesis flow for ODIN II [odin, yosys]
-
-    **Default:** odin
-
 .. option:: -top_module <TOP_MODULE>
 
     Specifies the name of the module in the design that should be considered as top
 
-.. option:: -coarsen
-    
-    Notifies ODIN II if the input BLIF is coarse-grained.
-
-    **Default:** False
-
-.. note::
-
-    A coarse-grained BLIF file is defined as a BLIF file inclduing unmapped cells with the Yosys internal cell (listed `here <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/b913727959e22ae7a535ac8b907d0aaa9a3eda3d/ODIN_II/SRC/enum_str.cpp#L402-L494>`_) format which are represented by the ``.subckt`` tag in coarse-grained BLIF.
-
-.. option:: -encode_names
-    
-    Enables ODIN II utilization of operation-type-encoded naming style for Yosys coarse-grained RTLIL nodes.
-    
-    .. code-block::
-
-        # example of a DFF subcircuit in the Yosys coarse-grained BLIF
-        .subckt $dff CLK=clk D=a Q=inst1.inst2.temp
-        .param CLK_POLARITY 1
-
-        .names inst1.inst2.temp o
-        1 1
-
-        # fine-grained BLIF file with enabled encode_names option for Odin-II partial mapper
-        .latch test^a test^inst1.inst2.temp^FF~0 re test^clk 3
-
-        .names test^inst1.inst2.temp^FF~0 test^o
-        1 1
-
-        # fine-grained BLIF file with disabled encode_names option for Odin-II partial mapper
-        .latch test^a test^$dff^FF~0 re test^clk 3
-
-        .names test^$dff^FF~0 test^o
-        1 1
-
-    **Default:** False
-
 .. option:: -yosys_script <YOSYS_SCRIPT>
 
     Supplies Yosys with a .ys script file (similar to Tcl script), including the synthesis steps.

vtr_flow/scripts/run_vtr_flow.py

@@ -332,42 +332,12 @@ def vtr_command_argparser(prog=None):
         dest="odin_config",
         help="Supplies Odin with a custom config file for optimizations.",
     )
-    odin.add_argument(
-        "-elaborator",
-        nargs=None,
-        default="odin",
-        dest="elaborator",
-        help="Specify the elaborator of the synthesis flow for Odin-II",
-    )
     odin.add_argument(
         "-top_module",
         default=None,
         dest="top_module",
         help="Specify the name of the module in the design that should be considered as top",
     )
-    odin.add_argument(
-        "-coarsen",
-        default=False,
-        action="store_true",
-        dest="coarsen",
-        help="Notify Odin if the input BLIF is coarse-grain",
-    )
-    odin.add_argument(
-        "-fflegalize",
-        default=False,
-        action="store_true",
-        dest="fflegalize",
-        help="Make flip-flops rising edge for coarse-grain input BLIFs in the techmap"
-        + "(Odin-II synthesis flow generates rising edge FFs by default)",
-    )
-    odin.add_argument(
-        "-encode_names",
-        default=False,
-        action="store_true",
-        dest="encode_names",
-        help="Enable Odin-II utilization of operation-type-encoded naming style for Yosys"
-        + " coarse-grained RTLIL nodes",
-    )
     #
     # YOSYS arguments
     #
@@ -712,8 +682,6 @@ def process_odin_args(args):
     odin_args["parser"] = args.parser
     odin_args["adder_type"] = args.adder_type
     odin_args["top_module"] = args.top_module
-    # odin_args["elaborator"] = args.elaborator
-    # odin_args["encode_names"] = args.encode_names
 
     if args.adder_cin_global:
         odin_args["adder_cin_global"] = True
@@ -724,12 +692,6 @@ def process_odin_args(args):
     if args.use_odin_simulation:
         odin_args["use_odin_simulation"] = True
 
-    # if args.coarsen:
-    #     odin_args["coarsen"] = True
-
-    # if args.fflegalize:
-    #     odin_args["fflegalize"] = True
-
     return odin_args