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unused args removed
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4 files changed

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ODIN_II/SRC/odin_ii.cpp

Lines changed: 0 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -460,16 +460,6 @@ void get_options(int argc, char** argv) {
460460
.nargs('+')
461461
.metavar("VERILOG_FILE");
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463-
input_grp.add_argument(global_args.input_files, "-s")
464-
.help("List of SystemVerilog HDL file")
465-
.nargs('+')
466-
.metavar("SYSTEMVERILOG_FILE");
467-
468-
input_grp.add_argument(global_args.input_files, "-u")
469-
.help("List of UHDM HDL file")
470-
.nargs('+')
471-
.metavar("UHDM_FILE");
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473463
input_grp.add_argument(global_args.blif_file, "-b")
474464
.help("BLIF file")
475465
.metavar("BLIF_FILE");
@@ -663,9 +653,6 @@ void get_options(int argc, char** argv) {
663653
a config file(-c)\n\t\
664654
a BLIF file(-b)\n\t\
665655
a Verilog file(-v)\n\t\
666-
a SystemVerilog file(-s)\n\t\
667-
an UHDM file(-u)\n\t\
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a TCL file including HDL designs(-S)\n\
669656
Unless is used for infrastructure directly\n");
670657
}
671658

@@ -683,10 +670,6 @@ void get_options(int argc, char** argv) {
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std::string arg_name = string_to_lower(global_args.input_files.argument_name());
684671
if (arg_name == "-v")
685672
configuration.input_file_type = file_type_e::VERILOG;
686-
else if (arg_name == "-s")
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configuration.input_file_type = file_type_e::SYSTEM_VERILOG;
688-
else if (arg_name == "-u")
689-
configuration.input_file_type = file_type_e::UHDM;
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else {
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// Unknown argument name, should have been already checked in the argparse library
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error_message(PARSE_ARGS, unknown_location,

doc/src/odin/dev_guide/testing.md

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
The ``verify_odin.sh`` script will simulate the microbenchmarks and a larger set of benchmark circuits.
44
These scripts use simulation results which have been verified against ModelSim.
55

6-
After you build Odin-II, run ``make test ELABORATOR=odin`` or ``make test`` to ensure that everything is working correctly on your system.
6+
After you build Odin-II, run ``make test`` to ensure that everything is working correctly on your system.
77
The ``verify_odin.sh`` also simulates the blif output, as well as simulating the verilog with and without the
88
architecture file.
99

@@ -32,4 +32,4 @@ You may now directly compare the vectors in the ``output_vectors`` file with tho
3232
> For simulation purposes, you may need to handle the ``GLOBAL_SIM_BASE_CLK`` signal in the ``input_vector`` by either adding this signal as an input signal to the top module or removing it from the ``input_vector`` file.
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3434
To add the verified vectors and circuit to an existing test set, move the Verilog file (eg: ``test_circuit.v``) to the test set folder.
35-
Next, move the ``input_vectors`` file to the test set folder, and rename it ``test_circuit_$ELABORATOR_input`` (`$ELABORATOR: odin, yosys`). Finally, move the ``output_vectors`` file to the test set folder and rename it ``test_circuit_$ELABORATOR_output``.
35+
Next, move the ``input_vectors`` file to the test set folder, and rename it ``test_circuit_odin_input``. Finally, move the ``output_vectors`` file to the test set folder and rename it ``test_circuit_odin_output``.

doc/src/vtr/run_vtr_flow.rst

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Original file line numberDiff line numberDiff line change
@@ -232,53 +232,10 @@ Detailed Command-line Options
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**Default:** 1
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.. option:: -elaborator <ELABORATOR>
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Specifies the elaborator of the synthesis flow for ODIN II [odin, yosys]
238-
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**Default:** odin
240-
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.. option:: -top_module <TOP_MODULE>
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243237
Specifies the name of the module in the design that should be considered as top
244238

245-
.. option:: -coarsen
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Notifies ODIN II if the input BLIF is coarse-grained.
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**Default:** False
250-
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.. note::
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253-
A coarse-grained BLIF file is defined as a BLIF file inclduing unmapped cells with the Yosys internal cell (listed `here <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/b913727959e22ae7a535ac8b907d0aaa9a3eda3d/ODIN_II/SRC/enum_str.cpp#L402-L494>`_) format which are represented by the ``.subckt`` tag in coarse-grained BLIF.
254-
255-
.. option:: -encode_names
256-
257-
Enables ODIN II utilization of operation-type-encoded naming style for Yosys coarse-grained RTLIL nodes.
258-
259-
.. code-block::
260-
261-
# example of a DFF subcircuit in the Yosys coarse-grained BLIF
262-
.subckt $dff CLK=clk D=a Q=inst1.inst2.temp
263-
.param CLK_POLARITY 1
264-
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.names inst1.inst2.temp o
266-
1 1
267-
268-
# fine-grained BLIF file with enabled encode_names option for Odin-II partial mapper
269-
.latch test^a test^inst1.inst2.temp^FF~0 re test^clk 3
270-
271-
.names test^inst1.inst2.temp^FF~0 test^o
272-
1 1
273-
274-
# fine-grained BLIF file with disabled encode_names option for Odin-II partial mapper
275-
.latch test^a test^$dff^FF~0 re test^clk 3
276-
277-
.names test^$dff^FF~0 test^o
278-
1 1
279-
280-
**Default:** False
281-
282239
.. option:: -yosys_script <YOSYS_SCRIPT>
283240

284241
Supplies Yosys with a .ys script file (similar to Tcl script), including the synthesis steps.

vtr_flow/scripts/run_vtr_flow.py

Lines changed: 0 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -332,42 +332,12 @@ def vtr_command_argparser(prog=None):
332332
dest="odin_config",
333333
help="Supplies Odin with a custom config file for optimizations.",
334334
)
335-
odin.add_argument(
336-
"-elaborator",
337-
nargs=None,
338-
default="odin",
339-
dest="elaborator",
340-
help="Specify the elaborator of the synthesis flow for Odin-II",
341-
)
342335
odin.add_argument(
343336
"-top_module",
344337
default=None,
345338
dest="top_module",
346339
help="Specify the name of the module in the design that should be considered as top",
347340
)
348-
odin.add_argument(
349-
"-coarsen",
350-
default=False,
351-
action="store_true",
352-
dest="coarsen",
353-
help="Notify Odin if the input BLIF is coarse-grain",
354-
)
355-
odin.add_argument(
356-
"-fflegalize",
357-
default=False,
358-
action="store_true",
359-
dest="fflegalize",
360-
help="Make flip-flops rising edge for coarse-grain input BLIFs in the techmap"
361-
+ "(Odin-II synthesis flow generates rising edge FFs by default)",
362-
)
363-
odin.add_argument(
364-
"-encode_names",
365-
default=False,
366-
action="store_true",
367-
dest="encode_names",
368-
help="Enable Odin-II utilization of operation-type-encoded naming style for Yosys"
369-
+ " coarse-grained RTLIL nodes",
370-
)
371341
#
372342
# YOSYS arguments
373343
#
@@ -712,8 +682,6 @@ def process_odin_args(args):
712682
odin_args["parser"] = args.parser
713683
odin_args["adder_type"] = args.adder_type
714684
odin_args["top_module"] = args.top_module
715-
# odin_args["elaborator"] = args.elaborator
716-
# odin_args["encode_names"] = args.encode_names
717685

718686
if args.adder_cin_global:
719687
odin_args["adder_cin_global"] = True
@@ -724,12 +692,6 @@ def process_odin_args(args):
724692
if args.use_odin_simulation:
725693
odin_args["use_odin_simulation"] = True
726694

727-
# if args.coarsen:
728-
# odin_args["coarsen"] = True
729-
730-
# if args.fflegalize:
731-
# odin_args["fflegalize"] = True
732-
733695
return odin_args
734696

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