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51 | 51 | #ifdef ODIN_USE_YOSYS |
52 | 52 | # include "kernel/yosys.h" // Yosys |
53 | 53 | USING_YOSYS_NAMESPACE |
54 | | -# define YOSYS_ELABORATION_ERROR \ |
55 | | - "\n\tERROR: Yosys failed to perform elaboration, " \ |
56 | | - "Please look at the log file for the failure cause or pass \'--show_yosys_log\' to Odin-II to see the logs.\n" |
57 | | -# define YOSYS_FORK_ERROR \ |
58 | | - "\n\tERROR: Yosys child process failed to be created\n" |
59 | | -#else |
60 | | -# define YOSYS_INSTALLATION_ERROR \ |
61 | | - "ERROR: It seems Yosys is not installed in the VTR repository." \ |
62 | | - " Please compile the VTR with (" ODIN_USE_YOSYS_STR ") flag.\n" |
63 | 54 | #endif |
64 | 55 |
|
65 | 56 | /** |
@@ -137,11 +128,31 @@ void YYosys::perform_elaboration() { |
137 | 128 | /* wait for the Yosys child process */ |
138 | 129 | auto yosys_status = -1; // the status of the Yosys fork |
139 | 130 | waitpid(0, &yosys_status, 0); |
140 | | - int yosys_exit_status = WEXITSTATUS(yosys_status); |
141 | | - |
142 | | - if (yosys_exit_status != 0) { |
143 | | - error_message(PARSER, unknown_location, "%s", YOSYS_ELABORATION_ERROR); |
| 131 | + /* check if Yosys exited abnormally */ |
| 132 | + if (!WIFEXITED(yosys_status)) { |
| 133 | + if (WIFSIGNALED(yosys_status)) { |
| 134 | + error_message(PARSER, unknown_location, |
| 135 | + "Yosys exited with signal %d - %s", |
| 136 | + WTERMSIG(yosys_status), |
| 137 | + YOSYS_ELABORATION_ERROR); |
| 138 | + } else if (WIFSTOPPED(yosys_status)) { |
| 139 | + error_message(PARSER, unknown_location, |
| 140 | + "Yosys stopped with signal %d - %s", |
| 141 | + WSTOPSIG(yosys_status), |
| 142 | + YOSYS_ELABORATION_ERROR); |
| 143 | + } else { |
| 144 | + error_message(PARSER, unknown_location, "%s", |
| 145 | + "Something strange just happened with Yosys child process.\n"); |
| 146 | + } |
| 147 | + } else { |
| 148 | + auto yosys_exit_status = WEXITSTATUS(yosys_status); |
| 149 | + if (yosys_exit_status != 0) |
| 150 | + error_message(PARSER, unknown_location, |
| 151 | + "Yosys exited with status %d - %s", |
| 152 | + yosys_exit_status, |
| 153 | + YOSYS_ELABORATION_ERROR); |
144 | 154 | } |
| 155 | + |
145 | 156 | /* Yosys successfully generated coarse-grain BLIF file */ |
146 | 157 | this->re_initialize_odin_globals(); |
147 | 158 | } |
@@ -197,6 +208,11 @@ void YYosys::init_yosys() { |
197 | 208 | yosys_setup(); |
198 | 209 | yosys_banner(); |
199 | 210 |
|
| 211 | +# ifdef YOSYS_SV_UHDM_PLUGIN |
| 212 | + /* Load SystemVerilog/UHDM plugins in the Yosys frontend */ |
| 213 | + run_pass(std::string("plugin -i systemverilog")); |
| 214 | +# endif |
| 215 | + |
200 | 216 | /* Read VTR baseline library first */ |
201 | 217 | run_pass(std::string("read_verilog -nomem2reg " + this->vtr_primitives_file)); |
202 | 218 | run_pass(std::string("setattr -mod -set keep_hierarchy 1 " + std::string(SINGLE_PORT_RAM_string))); |
@@ -249,9 +265,34 @@ void YYosys::execute() { |
249 | 265 | } else { |
250 | 266 | // Read the hardware decription Verilog circuits |
251 | 267 | // FOR loop enables include feature for Yosys+Odin (multiple Verilog input files) |
252 | | - for (auto verilog_circuit : this->verilog_circuits) |
253 | | - run_pass(std::string("read_verilog -sv -nolatches " + verilog_circuit)); |
254 | | - |
| 268 | + std::string aggregated_circuits; |
| 269 | + for (auto circuit : this->verilog_circuits) |
| 270 | + aggregated_circuits += circuit + " "; |
| 271 | + // Read Verilog/SystemVerilog/UHDM files based on their type, considering the SystemVerilog/UHDM plugins |
| 272 | +# ifdef YOSYS_SV_UHDM_PLUGIN |
| 273 | + /* Load SystemVerilog/UHDM plugins in the Yosys frontend */ |
| 274 | + switch (configuration.input_file_type) { |
| 275 | + case (file_type_e::_VERILOG): // fallthrough |
| 276 | + case (file_type_e::_VERILOG_HEADER): { |
| 277 | + run_pass(std::string("read_verilog -sv -nolatches " + aggregated_circuits)); |
| 278 | + break; |
| 279 | + } |
| 280 | + case (file_type_e::_SYSTEM_VERILOG): { |
| 281 | + run_pass(std::string("read_systemverilog -debug " + aggregated_circuits)); |
| 282 | + break; |
| 283 | + } |
| 284 | + case (file_type_e::_UHDM): { |
| 285 | + run_pass(std::string("read_uhdm -debug " + aggregated_circuits)); |
| 286 | + break; |
| 287 | + } |
| 288 | + default: { |
| 289 | + error_message(UTIL, unknown_location, |
| 290 | + "Invalid file type (%s) for Yosys+Odin-II synthesizer.", file_extension_strmap[configuration.input_file_type]); |
| 291 | + } |
| 292 | + } |
| 293 | +# else |
| 294 | + run_pass(std::string("read_verilog -sv -nolatches " + aggregated_circuits)); |
| 295 | +# endif |
255 | 296 | // Check whether cells match libraries and find top module |
256 | 297 | if (global_args.top_level_module_name.provenance() == argparse::Provenance::SPECIFIED) { |
257 | 298 | run_pass(std::string("hierarchy -check -top " + global_args.top_level_module_name.value() + " -purge_lib")); |
@@ -298,7 +339,7 @@ void YYosys::execute() { |
298 | 339 | run_pass(std::string("pmuxtree")); |
299 | 340 | // To possibly reduce word sizes by Yosys |
300 | 341 | run_pass(std::string("wreduce")); |
301 | | - // "-undirven" to ensure there is no wire without drive |
| 342 | + // "-undriven" to ensure there is no wire without drive |
302 | 343 | // -noff #potential option to remove all sdffXX and etc. Only dff will remain |
303 | 344 | // "opt_muxtree" removes dead branches, "opt_expr" performs const folding and |
304 | 345 | // removes "undef" from mux inputs and replace muxes with buffers and inverters |
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