add a new line after the end of golden_results file

Author: amin1377

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt

@@ -1,2 +1,2 @@
  arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  num_io	  num_LAB	  num_DSP	  num_M9K	  num_M144K	  num_PLL	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  routed_wirelength	  total_nets_routed	  total_connections_routed	  total_heap_pushes	  total_heap_pops	  logic_block_area_total	  logic_block_area_used	  routing_area_total	  routing_area_per_tile	  crit_path_route_success_iteration	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  route_mem	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  router_lookahead_mem	  router_lookahead_computation_time
- stratixiv_arch.timing.xml	  ucsb_152_tap_fir_stratixiv_arch_timing.blif	  common	  58.78	  vpr	  1.12 GiB	  	  42	  750	  0	  0	  0	  0	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  1171016	  13	  29	  26295	  20086	  1	  12166	  792	  39	  29	  1131	  LAB	  auto	  1047.5 MiB	  11.58	  73134	  1097.2 MiB	  8.64	  0.13	  5.09794	  -4680.59	  -4.09794	  2.56822	  4.90	  0.0239667	  0.0207817	  1.8203	  1.50657	  80255	  27932	  41672	  32788183	  2856931	  0	  0	  2.05958e+07	  18210.3	  17	  5.28804	  2.67454	  -5275.78	  -4.28804	  0	  0	  1103.1 MiB	  4.24	  3.17151	  2.69689	  1097.2 MiB	  12.22	 
+ stratixiv_arch.timing.xml	  ucsb_152_tap_fir_stratixiv_arch_timing.blif	  common	  58.78	  vpr	  1.12 GiB	  	  42	  750	  0	  0	  0	  0	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  1171016	  13	  29	  26295	  20086	  1	  12166	  792	  39	  29	  1131	  LAB	  auto	  1047.5 MiB	  11.58	  73134	  1097.2 MiB	  8.64	  0.13	  5.09794	  -4680.59	  -4.09794	  2.56822	  4.90	  0.0239667	  0.0207817	  1.8203	  1.50657	  80255	  27932	  41672	  32788183	  2856931	  0	  0	  2.05958e+07	  18210.3	  17	  5.28804	  2.67454	  -5275.78	  -4.28804	  0	  0	  1103.1 MiB	  4.24	  3.17151	  2.69689	  1097.2 MiB	  12.22