update golden result for tight floor plan

Author: zhaisitong

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt

@@ -1,2 +1,2 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	yosys_synth_time	max_yosys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-k6_frac_N10_40nm.xml	bigkey.blif	common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml	216.41	vpr	1.01 GiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	149	229	-1	-1	success	v8.0.0-6603-g178d2c87f-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 11.3.0 on Linux-5.15.0-52-generic x86_64	2022-10-28T17:49:03	virtual	/home/zhaisitong/worksapce/master/vtr-verilog-to-routing/vtr_flow/tasks	1056768	229	197	2152	2349	1	1011	575	16	16	256	io	auto	826.4 MiB	100.38	8105	1032.0 MiB	66.21	0.51	2.67358	-601.873	-2.67358	2.67358	1.43	0.0351485	0.0290178	5.8406	4.83522	-1	11422	11	1.05632e+07	8.03021e+06	4.24953e+06	16599.7	4.66	7.21807	6.08273	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+k6_frac_N10_40nm.xml	bigkey.blif	common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml	5.77	vpr	73.31 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	149	229	-1	-1	success	v8.0.0-6603-g178d2c87f	release IPO VTR_ASSERT_LEVEL=2	GNU 11.3.0 on Linux-5.15.0-52-generic x86_64	2022-10-28T12:34:49	virtual	/home/zhaisitong/worksapce/debug/vtr-verilog-to-routing/vtr_flow/tasks	75068	229	197	2152	2349	1	1011	575	16	16	256	io	auto	36.0 MiB	1.97	8105	73.3 MiB	1.34	0.01	2.67358	-601.873	-2.67358	2.67358	0.02	0.00228582	0.0019988	0.389356	0.335982	-1	11422	11	1.05632e+07	8.03021e+06	4.24953e+06	16599.7	0.16	0.520597	0.459658	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1