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vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5
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lines changed Original file line number Diff line number Diff line change 11regression_tests/vtr_reg_nightly_test5/vpr_ispd
22regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan
3- regression_tests/vtr_reg_nightly_test5/vpr_noc_2D_chain_topology
3+ regression_tests/vtr_reg_nightly_test5/vpr_noc_nearest_neighbor_topology
44regression_tests/vtr_reg_nightly_test5/vpr_noc_clique_topology
55regression_tests/vtr_reg_nightly_test5/vpr_noc_star_topology
Original file line number Diff line number Diff line change 33##############################################
44
55# Path to directory of circuits to use
6- circuits_dir=benchmarks/noc/Synthetic_Designs/complex_64_noc_2D_chain /
6+ circuits_dir=benchmarks/noc/Synthetic_Designs/complex_64_noc_nearest_neighbor /
77
88# Path to directory of architectures to use
99archs_dir=arch/noc/mesh_noc_topology
1010
1111# Add circuits to list to sweep
12- circuit_list_add=complex_64_noc_2D_chain .blif
12+ circuit_list_add=complex_64_noc_nearest_neighbor .blif
1313
1414# Add architectures to list to sweep
1515arch_list_add=stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml
@@ -24,5 +24,5 @@ qor_parse_file=qor_noc_spec.txt
2424pass_requirements_file=pass_requirements.txt
2525
2626# Script parameters
27- script_params =-starting_stage vpr --noc on --noc_routing_algorithm xy_routing --device "EP4SE820" --noc_flows_file ../../../../../../../../benchmarks/noc/Synthetic_Designs/complex_64_noc_2D_chain/complex_64_noc_2D_chain .flows
27+ script_params =-starting_stage vpr --noc on --noc_routing_algorithm xy_routing --device "EP4SE820" --noc_flows_file ../../../../../../../../benchmarks/noc/Synthetic_Designs/complex_64_noc_nearest_neighbor/complex_64_noc_nearest_neighbor .flows
2828
Original file line number Diff line number Diff line change 11arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency
2- stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_2D_chain .blif common 8560.06 vpr 7.77 GiB -1 2 -1 -1 success v8.0.0-6827-g874e0cb8d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2023-01-19T13:42:08 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/add_noc_testcases/vtr-verilog-to-routing/vtr_flow/tasks 8144244 2 32 245317 207097 1 127846 7926 220 162 35640 -1 EP4SE820 2807.4 MiB 400.67 1238130 7953.4 MiB 769.07 5.03 6.71786 -823307 -6.71786 6.71786 2196.38 0.600359 0.532866 91.0284 76.9373 154 1432666 41 0 0 3.59543e+08 10088.2 4213.30 388.018 328.35 1435190 17 353532 839730 444668516 43599148 7.3303 7.3303 -1.03553e+06 -7.3303 0 0 4.57197e+08 12828.2 437.18 75.13 30.7833 27.281 7.4e+07 6.28e-07
2+ stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_nearest_neighbor .blif common 8560.06 vpr 7.77 GiB -1 2 -1 -1 success v8.0.0-6827-g874e0cb8d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2023-01-19T13:42:08 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/add_noc_testcases/vtr-verilog-to-routing/vtr_flow/tasks 8144244 2 32 245317 207097 1 127846 7926 220 162 35640 -1 EP4SE820 2807.4 MiB 400.67 1238130 7953.4 MiB 769.07 5.03 6.71786 -823307 -6.71786 6.71786 2196.38 0.600359 0.532866 91.0284 76.9373 154 1432666 41 0 0 3.59543e+08 10088.2 4213.30 388.018 328.35 1435190 17 353532 839730 444668516 43599148 7.3303 7.3303 -1.03553e+06 -7.3303 0 0 4.57197e+08 12828.2 437.18 75.13 30.7833 27.281 7.4e+07 6.28e-07
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