Merge pull request #2261 from verilog-to-routing/noc_benchmark_design_final_2

Noc benchmark design final 2

Author: vaughnbetz

vtr_flow/arch/noc/mesh_noc_topology/stratixiv_arch.timing_small_with_a_embedded_mesh_noc_toplogy.xml

@@ -367,8 +367,6 @@ module adder_with_1_reg (
 	datab,
 	result);
 
-	input	  clk;
-	input	  clk_ena;
 	input	[17:0]  dataa;
 	input	[17:0]  datab;
 	output	[17:0]  result;
@@ -383,8 +381,6 @@ module multiplier_with_reg (
 	datab,
 	result);
 
-	input	  clk;
-	input	  clk_ena;
 	input	[17:0]  dataa;
 	input	[17:0]  datab;
 	output	[17:0]  result;
@@ -398,8 +394,6 @@ module one_register (
 	dataa,
 	result);
 
-	input	  clk;
-	input	  clk_ena;
 	input	[17:0]  dataa;
 	output	[17:0]  result;
 

vtr_flow/arch/noc/mesh_noc_topology/stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml

@@ -0,0 +1,5 @@
+<traffic_flows>
+
+	<single_flow src=".*noc_router_adapter_block_one.*" dst=".*noc_router_adapter_block_two.*" bandwidth="4e5" latency_cons="3e-9" />
+
+</traffic_flows>

vtr_flow/arch/noc/mesh_noc_topology/stratixiv_arch.timing_with_a_embedded_3X3_mesh_noc_topology_2.xml

@@ -0,0 +1,139 @@
+/*
+    Top level modules to instantiate an AXI handshake between two routers.
+    The design implements the following:
+        1) Traffic generator uses a FIR filter to generate data and pass it to master_interface.
+        2) Master interface sends data and valid signal that coming from traffic generator to the NoC.
+        3) Slave interface receives data and valid signal, passes the ready signal through NoC and data to the traffic processor.
+        4) Traffic Processor encrypts the data and passes it to the output. 
+
+*/
+module complex_noc_1D_chain (
+    clk,
+    reset,
+	data_out
+);
+
+parameter noc_dw = 32; //NoC Data Width
+parameter byte_dw = 8; 
+
+/*****************INPUT/OUTPUT Definition********************/
+input wire clk;
+input wire reset;
+
+output wire [noc_dw - 1:0] data_out;
+
+/*******************Internal Variables**********************/
+//traffic generator
+wire [noc_dw - 1 : 0] tg_data;
+wire tg_valid;
+
+//master interface
+wire [noc_dw -1 : 0] m_data;
+wire m_valid;
+wire m_ready;
+
+//NoC Adapter - Connected to slave interface
+wire [noc_dw - 1 : 0] na2_data;
+wire na2_valid;
+
+//slave interface
+wire [noc_dw -1 : 0] s_data;
+wire s_valid;
+wire s_ready;
+
+/*******************module instantiation********************/
+traffic_generator tg(
+    .clk(clk),
+    .reset(reset),
+    .tdata(tg_data),
+    .tvalid(tg_valid)
+);
+
+master_interface mi (
+	.clk(clk),
+	.reset(reset),
+	.tvalid_in(tg_valid),
+	.tdata_in(tg_data),
+	.tready(m_ready), 
+	.tdata_out(m_data),
+	.tvalid_out(m_valid),
+	.tstrb(),
+	.tkeep(),
+	.tid(),
+	.tdest(),
+	.tuser(),
+	.tlast()
+);
+
+noc_router_adapter_block noc_router_adapter_block_one(
+	.clk(clk),
+    .reset(reset),
+    .master_tready(1'd0),
+    .master_tdata(),
+	.master_tvalid(),
+    .master_tstrb(),
+    .master_tkeep(),
+    .master_tid(),
+    .master_tdest(),
+    .master_tuser(),
+    .master_tlast(),
+    .slave_tvalid(m_valid),
+    .slave_tready(m_ready), 
+    .slave_tdata(m_data),
+    .slave_tstrb(8'd0),
+    .slave_tkeep(8'd0),
+    .slave_tid(8'd0),
+    .slave_tdest(8'd0),
+    .slave_tuser(8'd0),
+    .slave_tlast(1'd0),
+
+);
+
+noc_router_adapter_block noc_router_adapter_block_two(
+	.clk(clk),
+    .reset(reset),
+    .master_tready(s_ready),
+    .master_tdata(na2_data),
+	.master_tvalid(na2_valid),
+    .master_tstrb(),
+    .master_tkeep(),
+    .master_tid(),
+    .master_tdest(),
+    .master_tuser(),
+    .master_tlast(),
+    .slave_tvalid(1'd0),
+    .slave_tready(), 
+    .slave_tdata(32'd0),
+    .slave_tstrb(8'd0),
+    .slave_tkeep(8'd0),
+    .slave_tid(8'd0),
+    .slave_tdest(8'd0),
+    .slave_tuser(8'd0),
+    .slave_tlast(1'd0),
+);
+
+slave_interface si(
+	.clk(clk),
+	.reset(reset),
+	.tvalid_in(na2_valid),
+	.tdata_in(na2_data),
+	.tready(s_ready),
+	.tdata_out(s_data),
+	.tvalid_out(s_valid),
+	.tstrb(8'd0),
+	.tkeep(8'd0),
+	.tid(8'd0),
+	.tdest(8'd0),
+	.tuser(8'd0),
+	.tlast(1'd0)
+);
+
+traffic_processor tp(
+	.clk(clk),
+	.reset(reset),
+	.tdata(s_data),
+	.tvalid(s_valid),
+	.o_enc(data_out)
+);
+
+endmodule

vtr_flow/arch/noc/mesh_noc_topology/stratixiv_arch.timing_with_a_embedded_4X4_mesh_noc_topology.xml

@@ -0,0 +1,56 @@
+/* This is the traffic generator module. This
+	generate data to be sent over the NoC to the
+	traffic processor module*/
+	
+module traffic_generator(
+    clk,
+    reset,
+    tdata,
+    tvalid
+);
+
+parameter noc_dw = 32; //NoC Data Width
+parameter byte_dw = 8; 
+parameter filter_dw = 18;
+parameter acc_const = 4;
+
+/*****************INPUT/OUTPUT Definition********************/
+input wire clk;
+input wire reset;
+
+output wire [noc_dw - 1 : 0] tdata;
+output wire tvalid;
+
+/*******************Internal Variables**********************/
+wire [filter_dw - 1 : 0] fir_out;
+reg  [filter_dw - 1 : 0] fir_in;
+reg fir_valid;
+
+/*******************module instantiation*******************/
+fir fir_filter(
+	.clk(clk),
+	.reset(reset),
+	.clk_ena(1'b1),
+	.i_valid(fir_valid),
+	.i_in(fir_in),
+	.o_valid(tvalid),
+	.o_out(fir_out)
+);
+
+/******************Sequential Logic*************************/
+always @ (posedge clk, posedge reset)
+begin
+	if(reset == 1'b1) begin
+	  fir_in <= 0;
+     fir_valid <= 1'b0;
+	end
+	else begin
+		fir_in <= fir_in + acc_const;
+		fir_valid <= 1'b1;
+	end
+end
+
+/*******************Output Logic***************************/
+assign tdata = {{14{1'b0}},fir_out};
+
+endmodule 

vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_10.v

@@ -0,0 +1,72 @@
+/* This is the traffic processor module. This
+	accepts data coming in from the NoC and 
+	encrypts it using sha algorithm
+*/
+
+module traffic_processor (
+	clk,
+	reset,
+	tdata,
+	tvalid,
+	o_enc
+);
+
+/*****************Parameter Declarations********************/
+parameter noc_dw = 32;
+
+/*****************INPUT/OUTPUT Definition*******************/
+input wire clk;
+input wire reset;
+input wire [noc_dw-1:0] tdata;
+input tvalid;
+
+output reg [noc_dw-1:0] o_enc;
+
+/*******************Internal Variables**********************/
+wire [noc_dw - 1 : 0] sha_out;
+wire [noc_dw - 1 : 0] sha2_out;
+
+
+/*******************module instantiation*******************/
+sha1 sha1_module
+(
+	.clk_i(clk),
+	.rst_i(reset),
+	.text_i(tdata),
+	.text_o(sha_out),
+	.cmd_i({{2{1'b0}},{2{tvalid}}}),
+	.cmd_w_i(tvalid),
+	.cmd_o()
+);
+
+sha1 sha2_module 
+(
+	.clk_i(clk),
+	.rst_i(reset),
+	.text_i(sha_out),
+	.text_o(sha2_out),
+	.cmd_i({{1{1'b0}},{2{tvalid}}}),
+	.cmd_w_i(tvalid), 
+	.cmd_o()
+);
+
+/******************Sequential Logic*************************/
+/*
+	This module will wait on the tvalid signal
+	to indicate whether data is available to read
+	in from the input.
+*/
+
+always @(posedge clk)
+begin
+	if (reset)begin
+			o_enc <= 0;
+		end
+	else begin
+			if (tvalid) begin
+				o_enc <= sha2_out;
+			end
+		end
+end
+		
+endmodule