Skip to content

Commit e1df2f4

Browse files
vanvughtvanvught
committed
Refactor and clean up GD32 library structure and code
Renamed and reorganized several source files for consistency (e.g., bkp.cpp to gd32_bkp.cpp, mac_address.cpp to gd32_mac_address.cpp), removed unused or redundant files (stack_debug.h, gd32_gpio_mode_set.cpp, uart0.cpp), and updated include guards and formatting across headers. Refactored DMA memcpy32 and SPI DMA I2S code for improved naming and clarity. Made minor code style and copyright updates, and fixed function and variable naming -> Google C++ Style Guide
1 parent 0eff9f8 commit e1df2f4

37 files changed

Lines changed: 227 additions & 359 deletions

‎lib-gd32/include/board/logic_analyzer.h‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -26,18 +26,18 @@
2626
#ifndef BOARD_LOGIC_ANALYZER_H_
2727
#define BOARD_LOGIC_ANALYZER_H_
2828

29-
#define LOGIC_ANALYZER_CH0_GPIO_PINx GPIO_PIN_6 // PA6
30-
#define LOGIC_ANALYZER_CH1_GPIO_PINx GPIO_PIN_14 // PB14
31-
#define LOGIC_ANALYZER_CH2_GPIO_PINx GPIO_PIN_15 // PB15
32-
#define LOGIC_ANALYZER_CH3_GPIO_PINx GPIO_PIN_11 // PA11
29+
#define LOGIC_ANALYZER_CH0_GPIO_PINx GPIO_PIN_15 // PB15
30+
#define LOGIC_ANALYZER_CH1_GPIO_PINx GPIO_PIN_11 // PA13
31+
#define LOGIC_ANALYZER_CH2_GPIO_PINx GPIO_PIN_15 // PA11
32+
//#define LOGIC_ANALYZER_CH3_GPIO_PINx GPIO_PIN_11 // PA11
3333
//#define LOGIC_ANALYZER_CH4_GPIO_PINx GPIO_PIN_9
3434
//#define LOGIC_ANALYZER_CH5_GPIO_PINx GPIO_PIN_13
3535
//#define LOGIC_ANALYZER_CH6_GPIO_PINx GPIO_PIN_11
3636
//#define LOGIC_ANALYZER_CH7_GPIO_PINx GPIO_PIN_15
3737

38-
#define LOGIC_ANALYZER_CH0_GPIOx GPIOA
39-
#define LOGIC_ANALYZER_CH1_GPIOx GPIOB
40-
#define LOGIC_ANALYZER_CH2_GPIOx GPIOB
38+
#define LOGIC_ANALYZER_CH0_GPIOx GPIOB
39+
#define LOGIC_ANALYZER_CH1_GPIOx GPIOA
40+
#define LOGIC_ANALYZER_CH2_GPIOx GPIOA
4141
#define LOGIC_ANALYZER_CH3_GPIOx GPIOA
4242
#define LOGIC_ANALYZER_CH4_GPIOx GPIOC
4343
#define LOGIC_ANALYZER_CH5_GPIOx GPIOC

‎lib-gd32/include/gd32.h‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,3 @@
1-
#ifndef GD32_H_
2-
#define GD32_H_
3-
4-
#define GD32_H_
51
/**
62
* @file gd32.h
73
*
@@ -26,6 +22,9 @@
2622
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
2723
* THE SOFTWARE.
2824
*/
25+
26+
#ifndef GD32_H_
27+
#define GD32_H_
2928

3029
#include <stdint.h>
3130

‎lib-gd32/include/gd32_adc.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,4 +32,4 @@ float Gd32AdcGetVref();
3232
float Gd32AdcGetVbat();
3333
#endif
3434

35-
#endif // GD32_ADC_H_
35+
#endif // GD32_ADC_H_

‎lib-gd32/include/gd32_board.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -92,4 +92,4 @@
9292
#define ENETx
9393
#endif
9494

95-
#endif // GD32_BOARD_H_
95+
#endif // GD32_BOARD_H_

‎lib-gd32/include/gd32_dma.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -242,4 +242,4 @@ template <uint32_t peripheral, dma_channel_enum channel, uint32_t nSource> inlin
242242
#error
243243
#endif
244244

245-
#endif /* GD32_DMA_H_ */
245+
#endif // GD32_DMA_H_

‎lib-gd32/include/gd32_dma_memcpy32.h‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -31,50 +31,50 @@
3131

3232
#include "gd32.h"
3333

34-
namespace dma
34+
namespace dma::memcpy32
3535
{
36-
void Memcpy32Init();
36+
void Init();
3737

38-
inline void Memcpy32(const void* destination, const void* source, uint32_t length)
38+
inline void StartDma(const void* destination, const void* source, uint32_t length)
3939
{
4040
assert((reinterpret_cast<uint32_t>(source) & 0x3) == 0);
4141
assert((reinterpret_cast<uint32_t>(destination) & 0x3) == 0);
4242

4343
#if !defined(GD32F4XX)
44-
uint32_t dmaCHCTL = DMA_CHCTL(DMA0, DMA_CH3);
45-
dmaCHCTL &= ~DMA_CHXCTL_CHEN;
46-
DMA_CHCTL(DMA0, DMA_CH3) = dmaCHCTL;
44+
uint32_t dma_chctl = DMA_CHCTL(DMA0, DMA_CH3);
45+
dma_chctl &= ~DMA_CHXCTL_CHEN;
46+
DMA_CHCTL(DMA0, DMA_CH3) = dma_chctl;
4747

4848
DMA_CHPADDR(DMA0, DMA_CH3) = reinterpret_cast<uint32_t>(source);
4949
DMA_CHMADDR(DMA0, DMA_CH3) = reinterpret_cast<uint32_t>(destination);
5050
DMA_CHCNT(DMA0, DMA_CH3) = (length & DMA_CHXCNT_CNT);
5151

52-
dmaCHCTL |= DMA_CHXCTL_CHEN;
53-
DMA_CHCTL(DMA0, DMA_CH3) = dmaCHCTL;
52+
dma_chctl |= DMA_CHXCTL_CHEN;
53+
DMA_CHCTL(DMA0, DMA_CH3) = dma_chctl;
5454
#else
55-
uint32_t dmaCHCTL = DMA_CHCTL(DMA1, DMA_CH0);
56-
dmaCHCTL &= ~DMA_CHXCTL_CHEN;
57-
DMA_CHCTL(DMA1, DMA_CH0) = dmaCHCTL;
55+
uint32_t dma_chctl = DMA_CHCTL(DMA1, DMA_CH0);
56+
dma_chctl &= ~DMA_CHXCTL_CHEN;
57+
DMA_CHCTL(DMA1, DMA_CH0) = dma_chctl;
5858

5959
DMA_INTC0(DMA1) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, DMA_CH0);
6060

6161
DMA_CHM0ADDR(DMA1, DMA_CH0) = reinterpret_cast<uint32_t>(destination);
6262
DMA_CHPADDR(DMA1, DMA_CH0) = reinterpret_cast<uint32_t>(source);
6363
DMA_CHCNT(DMA1, DMA_CH0) = length;
6464

65-
dmaCHCTL |= DMA_CHXCTL_CHEN;
66-
DMA_CHCTL(DMA1, DMA_CH0) = dmaCHCTL;
65+
dma_chctl |= DMA_CHXCTL_CHEN;
66+
DMA_CHCTL(DMA1, DMA_CH0) = dma_chctl;
6767
#endif
6868
}
6969

70-
inline bool Memcpy32IsActive()
70+
inline bool IsActive()
7171
{
7272
#if !defined(GD32F4XX)
7373
return DMA_CHCNT(DMA0, DMA_CH3) != 0;
7474
#else
7575
return DMA_CHCNT(DMA1, DMA_CH0) != 0;
7676
#endif
7777
}
78-
} // namespace dma
78+
} // namespace dma::memcpy32
7979

80-
#endif // GD32_DMA_MEMCPY32_H_
80+
#endif // GD32_DMA_MEMCPY32_H_

‎lib-gd32/include/gd32_enet.h‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@
4949
* - **GD32H7XX**: Similar to GD32F4XX but considers the Ethernet peripheral base address.
5050
*/
5151
#if defined(GD32F10X) || defined(GD32F20X)
52-
template <enet_descstate_enum info_get> uint32_t gd32_enet_desc_information_get(const enet_descriptors_struct* desc)
52+
template <enet_descstate_enum info_get> uint32_t Gd32EnetDescInformationGet(const enet_descriptors_struct* desc)
5353
{
5454
uint32_t reval = 0xFFFFFFFFU;
5555

@@ -87,7 +87,7 @@ template <enet_descstate_enum info_get> uint32_t gd32_enet_desc_information_get(
8787
return reval;
8888
}
8989
#elif defined(GD32F4XX)
90-
template <enet_descstate_enum info_get> uint32_t gd32_enet_desc_information_get(const enet_descriptors_struct* desc)
90+
template <enet_descstate_enum info_get> uint32_t Gd32EnetDescInformationGet(const enet_descriptors_struct* desc)
9191
{
9292
uint32_t reval = 0xFFFFFFFFU;
9393

@@ -130,7 +130,7 @@ template <enet_descstate_enum info_get> uint32_t gd32_enet_desc_information_get(
130130
return reval;
131131
}
132132
#elif defined(GD32H7XX)
133-
template <enet_descstate_enum info_get> uint32_t gd32_enet_desc_information_get(const enet_descriptors_struct* desc)
133+
template <enet_descstate_enum info_get> uint32_t Gd32EnetDescInformationGet(const enet_descriptors_struct* desc)
134134
{
135135
uint32_t reval = 0xFFFFFFFFU;
136136

@@ -184,7 +184,7 @@ template <enet_descstate_enum info_get> uint32_t gd32_enet_desc_information_get(
184184
* varies based on whether the target platform is GD32H7XX or not.
185185
*/
186186
#if defined(GD32H7XX)
187-
inline void gd32_enet_clear_dma_tx_flags_and_resume()
187+
inline void Gd32EnetClearDmaTxFlagsAndResume()
188188
{
189189
const auto dma_tbu_flag = (ENET_DMA_STAT(ENETx) & ENET_DMA_STAT_TBU);
190190
const auto dma_tu_flag = (ENET_DMA_STAT(ENETx) & ENET_DMA_STAT_TU);
@@ -196,7 +196,7 @@ inline void gd32_enet_clear_dma_tx_flags_and_resume()
196196
}
197197
}
198198
#else
199-
inline void gd32_enet_clear_dma_tx_flags_and_resume()
199+
inline void Gd32EnetClearDmaTxFlagsAndResume()
200200
{
201201
const auto kDmaTbuFlag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU);
202202
const auto kDmaTuFlag = (ENET_DMA_STAT & ENET_DMA_STAT_TU);
@@ -221,7 +221,7 @@ inline void gd32_enet_clear_dma_tx_flags_and_resume()
221221
* caused by the Rx buffer unavailable condition.
222222
*/
223223
#if defined(GD32H7XX)
224-
inline void gd32_enet_handle_rx_buffer_unavailable()
224+
inline void Gd32EnetHandleRxBufferUnavailable()
225225
{
226226
if (0 != (ENET_DMA_STAT(ENETx) & ENET_DMA_STAT_RBU))
227227
{
@@ -230,7 +230,7 @@ inline void gd32_enet_handle_rx_buffer_unavailable()
230230
}
231231
}
232232
#else
233-
inline void gd32_enet_handle_rx_buffer_unavailable()
233+
inline void Gd32EnetHandleRxBufferUnavailable()
234234
{
235235
if (0 != (ENET_DMA_STAT & ENET_DMA_STAT_RBU))
236236
{
@@ -247,7 +247,7 @@ inline void gd32_enet_reset_hash()
247247
ENET_MAC_HLL(ENETx) = 0;
248248
}
249249
#else
250-
inline void gd32_enet_reset_hash()
250+
inline void Gd32EnetResetHash()
251251
{
252252
ENET_MAC_HLH = 0;
253253
ENET_MAC_HLL = 0;

‎lib-gd32/include/gd32_gpio.h‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -321,8 +321,7 @@ template <uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin> inline void
321321
GPIO_AFSEL1(gpio_periph) = afrh;
322322
}
323323
#else
324-
template <uint32_t gpio_periph, uint32_t mode, uint32_t pin, uint32_t speed = GPIO_OSPEED_50MHZ>
325-
inline void gd32_gpio_init()
324+
template <uint32_t gpio_periph, uint32_t mode, uint32_t pin, uint32_t speed = GPIO_OSPEED_50MHZ> inline void gd32_gpio_init()
326325
{
327326
/* GPIO mode configuration */
328327
auto temp_mode = (mode & 0x0F);
@@ -392,4 +391,4 @@ inline void gd32_gpio_init()
392391
#endif
393392
#endif
394393

395-
#endif // GD32_GPIO_H_
394+
#endif // GD32_GPIO_H_

‎lib-gd32/include/gd32_millis.h‎

Lines changed: 13 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
* @file gd32_millis.h
33
*
44
*/
5-
/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org
5+
/* Copyright (C) 2024-2025 by Arjan van Vught mailto:info@gd32-dmx.org
66
*
77
* Permission is hereby granted, free of charge, to any person obtaining a copy
88
* of this software and associated documentation files (the "Software"), to deal
@@ -28,20 +28,21 @@
2828

2929
#include <cstdint>
3030

31-
#if defined (USE_FREE_RTOS)
32-
# include "FreeRTOS.h"
33-
# include "task.h"
31+
#if defined(USE_FREE_RTOS)
32+
#include "FreeRTOS.h"
33+
#include "task.h"
3434
#endif
3535

36-
inline uint32_t millis() {
37-
#if defined (CONFIG_HAL_USE_SYSTICK)
38-
extern volatile uint32_t gv_nSysTickMillis;
39-
return gv_nSysTickMillis;
40-
#elif defined (USE_FREE_RTOS)
41-
return xTaskGetTickCount();
36+
inline uint32_t millis()
37+
{
38+
#if defined(CONFIG_HAL_USE_SYSTICK)
39+
extern volatile uint32_t gv_nSysTickMillis;
40+
return gv_nSysTickMillis;
41+
#elif defined(USE_FREE_RTOS)
42+
return xTaskGetTickCount();
4243
#else
43-
uint32_t Timer6GetElapsedMilliseconds();
44-
return Timer6GetElapsedMilliseconds();
44+
uint32_t Timer6GetElapsedMilliseconds();
45+
return Timer6GetElapsedMilliseconds();
4546
#endif
4647
}
4748

‎lib-gd32/include/gd32_ptp.h‎

Lines changed: 51 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -30,69 +30,80 @@
3030

3131
#include "gd32.h"
3232

33-
namespace gd32 {
34-
namespace ptp {
33+
namespace gd32
34+
{
35+
namespace ptp
36+
{
3537
#if !defined(MCU_CLOCK_FREQ)
36-
# error MCU_CLOCK_FREQ is not defined
38+
#error MCU_CLOCK_FREQ is not defined
3739
#endif
3840
#if !defined(PTP_ACCARACY_NS)
39-
static constexpr uint8_t PTP_TICK = 20;
41+
static constexpr uint8_t PTP_TICK = 20;
4042
#else
41-
static constexpr uint8_t PTP_TICK = PTP_ACCARACY_NS;
43+
static constexpr uint8_t PTP_TICK = PTP_ACCARACY_NS;
4244
#endif
43-
static constexpr uint8_t ADJ_FREQ_BASE_INCREMENT = static_cast<uint8_t>((PTP_TICK * static_cast<uint64_t>(1ULL << 31) / 1E9) + 0.5f);
44-
static constexpr uint32_t ADJ_FREQ_BASE_ADDEND = (static_cast<uint64_t>(1ULL << 63) / AHB_CLOCK_FREQ) / ADJ_FREQ_BASE_INCREMENT;
45-
static constexpr int32_t ADJ_FREQ_MAX = 5120000;
46-
47-
struct time_t {
48-
int32_t tv_sec;
49-
int32_t tv_nsec;
45+
inline constexpr uint8_t ADJ_FREQ_BASE_INCREMENT = static_cast<uint8_t>((PTP_TICK * static_cast<uint64_t>(1ULL << 31) / 1E9) + 0.5f);
46+
inline constexpr uint32_t ADJ_FREQ_BASE_ADDEND = (static_cast<uint64_t>(1ULL << 63) / AHB_CLOCK_FREQ) / ADJ_FREQ_BASE_INCREMENT;
47+
inline constexpr int32_t ADJ_FREQ_MAX = 5120000;
48+
49+
struct time_t
50+
{
51+
int32_t tv_sec;
52+
int32_t tv_nsec;
5053
};
5154

52-
struct ptptime {
53-
uint32_t tv_sec;
54-
uint32_t tv_nsec;
55+
struct ptptime
56+
{
57+
uint32_t tv_sec;
58+
uint32_t tv_nsec;
5559
};
56-
} // namespace ptp
60+
} // namespace ptp
5761

58-
inline uint32_t ptp_nanosecond_2_subsecond(const uint32_t nanosecond) {
59-
uint64_t val = nanosecond * 0x80000000Ull;
60-
val /= 1000000000U;
61-
return static_cast<uint32_t>(val);
62+
inline uint32_t ptp_nanosecond_2_subsecond(const uint32_t nanosecond)
63+
{
64+
uint64_t val = nanosecond * 0x80000000Ull;
65+
val /= 1000000000U;
66+
return static_cast<uint32_t>(val);
6267
}
6368

64-
inline uint32_t ptp_subsecond_2_nanosecond(const uint32_t subsecond) {
65-
uint64_t val = subsecond * 1000000000Ull;
66-
val >>= 31U;
67-
return (uint32_t) val;
69+
inline uint32_t ptp_subsecond_2_nanosecond(const uint32_t subsecond)
70+
{
71+
uint64_t val = subsecond * 1000000000Ull;
72+
val >>= 31U;
73+
return (uint32_t)val;
6874
}
6975

70-
inline void normalize_time(ptp::time_t *r) {
71-
r->tv_sec += r->tv_nsec / 1000000000;
72-
r->tv_nsec -= r->tv_nsec / 1000000000 * 1000000000;
73-
74-
if (r->tv_sec > 0 && r->tv_nsec < 0) {
75-
r->tv_sec -= 1;
76-
r->tv_nsec += 1000000000;
77-
} else if (r->tv_sec < 0 && r->tv_nsec > 0) {
78-
r->tv_sec += 1;
79-
r->tv_nsec -= 1000000000;
80-
}
76+
inline void normalize_time(ptp::time_t* r)
77+
{
78+
r->tv_sec += r->tv_nsec / 1000000000;
79+
r->tv_nsec -= r->tv_nsec / 1000000000 * 1000000000;
80+
81+
if (r->tv_sec > 0 && r->tv_nsec < 0)
82+
{
83+
r->tv_sec -= 1;
84+
r->tv_nsec += 1000000000;
85+
}
86+
else if (r->tv_sec < 0 && r->tv_nsec > 0)
87+
{
88+
r->tv_sec += 1;
89+
r->tv_nsec -= 1000000000;
90+
}
8191
}
8292

83-
inline void sub_time(struct ptp::time_t *r, const struct ptp::time_t *x, const struct ptp::time_t *y) {
93+
inline void sub_time(struct ptp::time_t* r, const struct ptp::time_t* x, const struct ptp::time_t* y)
94+
{
8495
r->tv_sec = x->tv_sec - y->tv_sec;
8596
r->tv_nsec = x->tv_nsec - y->tv_nsec;
8697

8798
normalize_time(r);
8899
}
89100

90-
} // namespace gd32
101+
} // namespace gd32
91102

92103
void gd32_ptp_start();
93-
void gd32_ptp_get_time(gd32::ptp::ptptime *ptp_time);
94-
void gd32_ptp_set_time(const gd32::ptp::ptptime *ptp_time);
95-
void gd32_ptp_update_time(const gd32::ptp::time_t *ptp_time);
104+
void gd32_ptp_get_time(gd32::ptp::ptptime* ptp_time);
105+
void gd32_ptp_set_time(const gd32::ptp::ptptime* ptp_time);
106+
void gd32_ptp_update_time(const gd32::ptp::time_t* ptp_time);
96107
bool gd32_adj_frequency(const int32_t adjust_pbb);
97108

98109
#endif /* GD32_PTP_H_ */

0 commit comments

Comments
 (0)