Skip to content

Commit 784842c

Browse files
thor2002rothor2002ro
committed
[v4,0/9] Add ASPEED PCIe Root Complex support
https://patchwork.kernel.org/project/linux-pci/cover/20251027095825.181161-1-jacky_chou@aspeedtech.com/
1 parent ab8b30d commit 784842c

15 files changed

Lines changed: 1664 additions & 0 deletions

File tree

‎Documentation/devicetree/bindings/pci/aspeed,ast2600-pcie.yaml‎

Lines changed: 168 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,168 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/pci/aspeed,ast2600-pcie.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: ASPEED PCIe Root Complex Controller
8+
9+
maintainers:
10+
- Jacky Chou <jacky_chou@aspeedtech.com>
11+
12+
description:
13+
The ASPEED PCIe Root Complex controller provides PCI Express Root Complex
14+
functionality for ASPEED SoCs, such as the AST2600 and AST2700.
15+
This controller enables connectivity to PCIe endpoint devices, supporting
16+
memory and I/O windows, MSI and legacy interrupts, and integration with
17+
the SoC's clock, reset, and pinctrl subsystems. On AST2600, the PCIe Root
18+
Port device number is always 8.
19+
20+
properties:
21+
compatible:
22+
enum:
23+
- aspeed,ast2600-pcie
24+
- aspeed,ast2700-pcie
25+
26+
reg:
27+
maxItems: 1
28+
29+
ranges:
30+
minItems: 2
31+
maxItems: 2
32+
33+
interrupts:
34+
maxItems: 1
35+
description: IntX and MSI interrupt
36+
37+
resets:
38+
items:
39+
- description: PCIe controller reset
40+
41+
reset-names:
42+
items:
43+
- const: h2x
44+
45+
aspeed,ahbc:
46+
$ref: /schemas/types.yaml#/definitions/phandle
47+
description:
48+
Phandle to the ASPEED AHB Controller (AHBC) syscon node.
49+
This reference is used by the PCIe controller to access
50+
system-level configuration registers related to the AHB bus.
51+
To enable AHB access for the PCIe controller.
52+
53+
aspeed,pciecfg:
54+
$ref: /schemas/types.yaml#/definitions/phandle
55+
description:
56+
Phandle to the ASPEED PCIe configuration syscon node.
57+
This reference allows the PCIe controller to access
58+
SoC-specific PCIe configuration registers. There are the others
59+
functions such PCIe RC and PCIe EP will use this common register
60+
to configure the SoC interfaces.
61+
62+
legacy-interrupt-controller:
63+
description: Interrupt controller node for handling INTx.
64+
type: object
65+
properties:
66+
'#address-cells':
67+
const: 0
68+
'#interrupt-cells':
69+
const: 1
70+
interrupt-controller: true
71+
72+
required:
73+
- '#address-cells'
74+
- '#interrupt-cells'
75+
- interrupt-controller
76+
77+
additionalProperties: false
78+
79+
allOf:
80+
- $ref: /schemas/pci/pci-host-bridge.yaml#
81+
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
82+
- if:
83+
properties:
84+
compatible:
85+
contains:
86+
const: aspeed,ast2600-pcie
87+
then:
88+
required:
89+
- aspeed,ahbc
90+
else:
91+
properties:
92+
aspeed,ahbc: false
93+
- if:
94+
properties:
95+
compatible:
96+
contains:
97+
const: aspeed,ast2700-pcie
98+
then:
99+
required:
100+
- aspeed,pciecfg
101+
else:
102+
properties:
103+
aspeed,pciecfg: false
104+
105+
required:
106+
- reg
107+
- interrupts
108+
- bus-range
109+
- ranges
110+
- resets
111+
- reset-names
112+
- msi-controller
113+
- interrupt-map-mask
114+
- interrupt-map
115+
- legacy-interrupt-controller
116+
117+
unevaluatedProperties: false
118+
119+
examples:
120+
- |
121+
#include <dt-bindings/interrupt-controller/arm-gic.h>
122+
#include <dt-bindings/clock/ast2600-clock.h>
123+
124+
pcie0: pcie@1e770000 {
125+
compatible = "aspeed,ast2600-pcie";
126+
device_type = "pci";
127+
reg = <0x1e770000 0x100>;
128+
#address-cells = <3>;
129+
#size-cells = <2>;
130+
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
131+
bus-range = <0x00 0xff>;
132+
133+
ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000
134+
0x02000000 0x0 0x60000000 0x60000000 0x0 0x20000000>;
135+
136+
resets = <&syscon ASPEED_RESET_H2X>;
137+
reset-names = "h2x";
138+
pinctrl-0 = <&pinctrl_pcierc1_default>;
139+
pinctrl-names = "default";
140+
141+
#interrupt-cells = <1>;
142+
msi-controller;
143+
144+
aspeed,ahbc = <&ahbc>;
145+
146+
interrupt-map-mask = <0 0 0 7>;
147+
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
148+
<0 0 0 2 &pcie_intc0 1>,
149+
<0 0 0 3 &pcie_intc0 2>,
150+
<0 0 0 4 &pcie_intc0 3>;
151+
legacy-interrupt-controller {
152+
interrupt-controller;
153+
#address-cells = <0>;
154+
#interrupt-cells = <1>;
155+
};
156+
157+
pcie@8,0 {
158+
reg = <0x804000 0 0 0 0>;
159+
#address-cells = <3>;
160+
#size-cells = <2>;
161+
device_type = "pci";
162+
resets = <&syscon ASPEED_RESET_PCIE_RC_O>;
163+
reset-names = "perst";
164+
clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
165+
phys = <&pcie_phy1>;
166+
ranges;
167+
};
168+
};

‎Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,42 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/phy/aspeed,ast2600-pcie-phy.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: ASPEED PCIe PHY
8+
9+
maintainers:
10+
- Jacky Chou <jacky_chou@aspeedtech.com>
11+
12+
description:
13+
The ASPEED PCIe PHY provides the physical layer functionality for PCIe
14+
controllers in the SoC.
15+
16+
properties:
17+
compatible:
18+
items:
19+
- enum:
20+
- aspeed,ast2600-pcie-phy
21+
- aspeed,ast2700-pcie-phy
22+
23+
reg:
24+
maxItems: 1
25+
26+
"#phy-cells":
27+
const: 0
28+
29+
required:
30+
- compatible
31+
- reg
32+
- "#phy-cells"
33+
34+
additionalProperties: false
35+
36+
examples:
37+
- |
38+
phy@1e6ed200 {
39+
compatible = "aspeed,ast2600-pcie-phy";
40+
reg = <0x1e6ed200 0x100>;
41+
#phy-cells = <0>;
42+
};

‎Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -141,6 +141,7 @@ additionalProperties:
141141
- NRTS3
142142
- NRTS4
143143
- OSCCLK
144+
- PCIERC1
144145
- PEWAKE
145146
- PWM0
146147
- PWM1
@@ -369,6 +370,7 @@ additionalProperties:
369370
- NRTS3
370371
- NRTS4
371372
- OSCCLK
373+
- PCIERC1
372374
- PEWAKE
373375
- PWM0
374376
- PWM1

‎MAINTAINERS‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3836,6 +3836,17 @@ S: Maintained
38363836
F: Documentation/devicetree/bindings/media/aspeed,video-engine.yaml
38373837
F: drivers/media/platform/aspeed/
38383838

3839+
ASPEED PCIE CONTROLLER DRIVER
3840+
M: Jacky Chou <jacky_chou@aspeedtech.com>
3841+
L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
3842+
L: linux-pci@vger.kernel.org
3843+
S: Maintained
3844+
F: Documentation/devicetree/bindings/pci/aspeed,ast2600-pcie.yaml
3845+
F: Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml
3846+
F: Documentation/devicetree/bindings/soc/aspeed/aspeed,ast2700-pcie-cfg.yaml
3847+
F: drivers/pci/controller/pcie-aspeed.c
3848+
F: drivers/phy/aspeed/pcie-phy-aspeed.c
3849+
38393850
ASUS EC HARDWARE MONITOR DRIVER
38403851
M: Eugene Shalygin <eugene.shalygin@gmail.com>
38413852
L: linux-hwmon@vger.kernel.org

‎arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,11 @@
22
// Copyright 2019 IBM Corp.
33

44
&pinctrl {
5+
pinctrl_pcierc1_default: pcierc1-default {
6+
function = "PCIERC1";
7+
groups = "PCIERC1";
8+
};
9+
510
pinctrl_adc0_default: adc0_default {
611
function = "ADC0";
712
groups = "ADC0";

‎arch/arm/boot/dts/aspeed/aspeed-g6.dtsi‎

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -379,6 +379,60 @@
379379
quality = <100>;
380380
};
381381

382+
pcie_phy1: phy@1e6ed200 {
383+
compatible = "aspeed,ast2600-pcie-phy";
384+
reg = <0x1e6ed200 0x100>;
385+
#phy-cells = <0>;
386+
};
387+
388+
pcie0: pcie@1e770000 {
389+
compatible = "aspeed,ast2600-pcie";
390+
device_type = "pci";
391+
reg = <0x1e770000 0x100>;
392+
#address-cells = <3>;
393+
#size-cells = <2>;
394+
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
395+
bus-range = <0x00 0xff>;
396+
397+
ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000
398+
0x02000000 0x0 0x60000000 0x60000000 0x0 0x20000000>;
399+
400+
status = "disabled";
401+
402+
resets = <&syscon ASPEED_RESET_H2X>;
403+
reset-names = "h2x";
404+
pinctrl-0 = <&pinctrl_pcierc1_default>;
405+
pinctrl-names = "default";
406+
407+
#interrupt-cells = <1>;
408+
msi-controller;
409+
410+
aspeed,ahbc = <&ahbc>;
411+
412+
interrupt-map-mask = <0 0 0 7>;
413+
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
414+
<0 0 0 2 &pcie_intc0 1>,
415+
<0 0 0 3 &pcie_intc0 2>,
416+
<0 0 0 4 &pcie_intc0 3>;
417+
pcie_intc0: legacy-interrupt-controller {
418+
interrupt-controller;
419+
#address-cells = <0>;
420+
#interrupt-cells = <1>;
421+
};
422+
423+
pcie@8,0 {
424+
reg = <0x804000 0 0 0 0>;
425+
#address-cells = <3>;
426+
#size-cells = <2>;
427+
device_type = "pci";
428+
resets = <&syscon ASPEED_RESET_PCIE_RC_O>;
429+
reset-names = "perst";
430+
clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
431+
phys = <&pcie_phy1>;
432+
ranges;
433+
};
434+
};
435+
382436
gfx: display@1e6e6000 {
383437
compatible = "aspeed,ast2600-gfx", "syscon";
384438
reg = <0x1e6e6000 0x1000>;

‎drivers/pci/controller/Kconfig‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,22 @@ config PCI_VERSATILE
5858
bool "ARM Versatile PB PCI controller"
5959
depends on ARCH_VERSATILE || COMPILE_TEST
6060

61+
config PCIE_ASPEED
62+
bool "ASPEED PCIe controller"
63+
depends on ARCH_ASPEED || COMPILE_TEST
64+
depends on OF
65+
depends on PCI_MSI
66+
select IRQ_MSI_LIB
67+
help
68+
Enable this option to support the PCIe controller found on ASPEED
69+
SoCs.
70+
71+
This driver provides initialization and management for PCIe
72+
Root Complex functionality, including interrupt and MSI support.
73+
74+
Select Y if your platform uses an ASPEED SoC and requires PCIe
75+
connectivity.
76+
6177
config PCIE_BRCMSTB
6278
tristate "Broadcom Brcmstb PCIe controller"
6379
depends on ARCH_BRCMSTB || ARCH_BCM2835 || ARCH_BCMBCA || \

‎drivers/pci/controller/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@ obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
3939
obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
4040
obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o
4141
obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o
42+
obj-$(CONFIG_PCIE_ASPEED) += pcie-aspeed.o
4243

4344
# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
4445
obj-y += dwc/

0 commit comments

Comments
 (0)