DRC errors

[ThVerg]

Hey sir @thesourcerer8, i recently found your repo and as my first experiment with it, i was trying to build the cells from SKY130. But im getting DRC errors and errors in general. Is this expected?

Thank you very much for your time.

[thesourcerer8]

I haven't tried SKY130 for some time. There is currently one known bug in the truthtable generator, which causes empty functions, which could be the cause for the "Supplied boolean function and simulation are inconsistent". There are a few bugs in the .cell files, and some .cell files are generally experimental. In general there is always the possibility for failure in the routing and placement stage, e.g. due to congestion. So to some extent, this is expected, and whenever we have time we are working to improve the situation. If you can help and solve one or more of the issues, this would be very much appreciated.

[thesourcerer8]

Oh, and sometimes we get LVS errors from lclayout which seem to be wrong. Ah, sorry, now I finally noticed that you were asking for the DRC errors specifically. Hmm, good question, I haven't taken a look at Sky130 for quite some time, so I am not sure about those.

[thesourcerer8]

One thing you have to keep in mind is that we have to use a slightly different DRC rule deck than is normally used for normal IP blocks. E.g. we have to disable the metal1/metal2 minimum area checks, since they dont make sense for standard cells.

[ThVerg]

Questions:

1. Which Technology inside the repo is in the best condition?
2. Have you ever tried importing an "extended" cell library to Librelane (since these Technologies are supported there) (obviously integration will need changes)?