From 0109c9aa3e107cd2b52cea8ba1b84dfc84f35e9b Mon Sep 17 00:00:00 2001 From: Tomasz Leman Date: Mon, 15 Dec 2025 15:45:41 +0100 Subject: [PATCH] west.yml: update zephyr to 7c67dea76a9 Total of 759 commits. Changes include: 7c67dea76a9 intel_adsp: common: gdbstub: Fix compilation DEBUG_SLOT_MANAGER=n ebb5625bee8 intel_adsp: Add debug slot manager 2ce9d5f5e3c soc: intel_adsp: tools: cavstool.py: Look up the shell slot by type 8cb287a411e intel_adsp: debug_window: Describe the partial slot in page0 c7dd9d79bdf intel_adsp: kconfig: Increase the default size of MEMORY_WIN_2_SIZE 81666a32757 intel_adsp: common: gdbstub: Correct z_gdb_backend_init() return type 3b7b2aef96c drivers: dai: intel: ssp: add get_properties_copy support 05069845d4d drivers: dai: make user-space support build-time selectable fa2c904266a drivers: dai: add get_properties_copy() method 81e37ad4e85 drivers: dai: add ability to use dai.h from user threads 701cbfbc235 xtensa: mmu: may need to copy entries during L2 table dup 8d0103b4ad8 xtensa: mmu: spin lock for counter manipulation 3e339780782 cache: deprecate CONFIG_DOUBLEMAP 0540d274c0d xtensa: remove CONFIG_XTENSA_RPO_CACHE a82a09a3148 soc: intel_adsp: SoC specific cached/uncached regions support 5fefc8b8b82 xtensa: cache: guard kconfig CONFIG_XTENSA_{UN,}CACHED_REGION a8c1df6b807 cache: adds CONFIG_SOC_CACHE 169304813a1 cache: move arch_mem_coherent() into cache subsys a0a529aecc2 soc: intel_adsp: move ARCH_XTENSA_SET_RPO_TLB inside 06b462bdf69 soc: intel_adsp: add CONFIG_INTEL_ADSP_MEMORY_IS_MIRRORED b90b396e647 soc: intel_adsp/ace: move included linker script to include dir 301abd86309 xtensa: imply CONFIG_ARCH_HAS_RESERVED_PAGE_FRAMES if MMU 48537aeb1f0 xtensa: CONFIG_ARCH_HAS_USERSPACE should be in arch layer c11b666ab47 soc: intel_adsp/ace: remove secondary boot flow kconfig 27b1c3138f4 xtensa: mmu: remove CONFIG_XTENSA_MMU_DOUBLE_MAP 2e1b4de6d77 soc: intel_adsp/ace: rework MMU mapping array fdc2e884358 soc: intel_adsp/ace: don't use default MMU mappings 1bc72e68c6c xtensa: mmu: allow SoC to override default mappings 31428237dc3 soc: intel_adsp/ace: move Xtensa HiFi kconfigs to each SoC 04dd427bf1a xtensa: cleanup crt1.S Signed-off-by: Tomasz Leman --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 0bd10446385e..02ae93333d01 100644 --- a/west.yml +++ b/west.yml @@ -43,7 +43,7 @@ manifest: - name: zephyr repo-path: zephyr - revision: 769ba82aa5ec482af0c4649ba075065e901fbe69 + revision: 7c67dea76a9081f790766391cec1ac1302eec842 remote: zephyrproject # Import some projects listed in zephyr/west.yml@revision