pixel_pcb_r0-cache.lib

EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# MK20DX256VLH7
#
DEF MK20DX256VLH7 U 0 40 Y Y 1 F N
F0 "U" 0 -100 50 H V C CNN
F1 "MK20DX256VLH7" 0 1050 50 H V C CNN
F2 "MODULE" 0 950 50 H I C CNN
F3 "DOCUMENTATION" 0 950 50 H I C CNN
DRAW
S -3150 -2700 3600 2700 1 0 0 N
X PTE0\ADC1_SE4a\UART1_TX\I2C1_SDA\RTC_CLKOUT 1 3900 -2550 300 L 50 50 1 1 O C
X PTE1\LLWU_P0\ADC1_SE5a\UART1_RX 2 -3450 2300 300 R 50 50 1 1 B
X VDD 3 150 3000 300 D 50 50 1 1 W
X VSS 4 -150 -3000 300 U 50 50 1 1 W
X USB0_DP 5 -3450 450 300 R 50 50 1 1 B
X USB0_DM 6 -3450 300 300 R 50 50 1 1 B
X VOUT33 7 850 3000 300 D 50 50 1 1 O
X VREGIN 8 -950 3000 300 D 50 50 1 1 B
X PGA0_DP\ADC0_DP0\ADC1_DP3 9 -3450 1850 300 R 50 50 1 1 B
X PGA0_DM\ADC0_DM0\ADC1_DM3 10 -3450 1700 300 R 50 50 1 1 B
X EXTAL32 20 -3450 -1800 300 R 50 50 1 1 B
X VDD 30 -50 3000 300 D 50 50 1 1 W
X PTB17\TSI0_CH10\UART0_TX\FB_AD16\EWM_OUT_b 40 3900 -900 300 L 50 50 1 1 O
X PTC5\LLWU_P9\SPI0_SCK\LPTMR0_ALT2\I2S0_RXD0\FB_AD10\CMP0_OUT 50 3900 300 300 L 50 50 1 1 O
X PTD3\SPI0_SIN\UART2_TX\FB_AD3 60 3900 1800 300 L 50 50 1 1 B
X PGA1_DP\ADC1_DP0\ADC0_DP3 11 -3450 1550 300 R 50 50 1 1 B
X VBAT 21 -1500 3000 300 D 50 50 1 1 B
X VSS 31 50 -3000 300 U 50 50 1 1 W
X PTB18\TSI0_CH11\CAN0_TX\FTM2_CH0\I2S0_TX_BCLK\FB_AD15\FTM2_QD_PHA 41 3900 -750 300 L 50 50 1 1 B C
X PTC6\LLWU_P10\CMP0_IN0\SPI0_SOUT\PDB0_EXTRG\I2S0_RX_BCLK\FB_AD9\I2S0_MCLK 51 3900 450 300 L 50 50 1 1 O C
X PTD4\LLWU_P14\SPI0_PCS1\UART0_RTS_b\FTM0_CH4\FB_AD2\EWM_IN 61 3900 1950 300 L 50 50 1 1 B
X PGA1_DM\ADC1_DM0\ADC0_DM3 12 -3450 1400 300 R 50 50 1 1 B
X PTA0\JTAG_TCLK\SWD_CLK\EZP_CLK\TSI0_CH1\UART0_CTS_b\UART0_COL_b\FTM0_CH5 22 -3450 -2100 300 R 50 50 1 1 B C
X PTA18\EXTAL0\FTM0_FLT2\FTM_CLKIN0 32 -3450 -500 300 R 50 50 1 1 B C
X PTB19\TSI0_CH12\CAN0_RX\FTM2_CH1\I2S0_TX_FS\FB_OE_b\FTM2_QD_PHB 42 3900 -600 300 L 50 50 1 1 B
X PTC7\CMP0_IN1\SPI0_SIN\USB_SOF_OUT\I2S0_RX_FS\FB_AD8 52 3900 600 300 L 50 50 1 1 O
X PTD5\ADC0_SE6b\SPI0_PCS2\UART0_CTS_b\UART0_COL_b\FTM0_CH5\FB_AD1\EWM_OUT_b 62 3900 2100 300 L 50 50 1 1 O
X VDDA 13 50 3000 300 D 50 50 1 1 W
X PTA1\JTAG_TDI\EZP_DI\TSI0_CH2\UART0_RX 23 -3450 -2250 300 R 50 50 1 1 B
X PTA19\XTAL0\FTM1_FLT0\FTM_CLKIN1\LPTMR0_ALT1 33 3900 -1800 300 L 50 50 1 1 B C
X PTC0\ADC0_SE14\TSI0_CH13\SPI0_PCS4\PDB0_EXTRG\FB_AD14\I2S0_TXD1 43 3900 -450 300 L 50 50 1 1 B
X PTC8\ADC1_SE4b\CMP0_IN2\I2S0_MCLK\FB_AD7 53 3900 750 300 L 50 50 1 1 B C
X PTD6\LLWU_P15\ADC0_SE7b\SPI0_PCS3\UART0_RX\FTM0_CH6\FB_AD0\FTM0_FLT0 63 3900 2250 300 L 50 50 1 1 B
X VREFH 14 -1950 3000 300 D 50 50 1 1 B
X PTA2\JTAG_TDO\TRACE_SWO\EZP_DO\TSI0_CH3\UART0_TX\FTM0_CH7 24 -3450 -2400 300 R 50 50 1 1 B
X RESET_b 34 -3450 -1300 300 R 50 50 1 1 B
X PTC1\LLWU_P6\ADC0_SE15\TSI0_CH140\SPI0_PCS3\UART1_RTS_b\FTM0_CH0\FB_AD13\I2S0_TXD0 44 3900 -300 300 L 50 50 1 1 B
X PTC9\ADC1_SE5b\CMP0_IN3\I2S0_RX_BCLK\FB_AD6\FTM2_FLT0 54 3900 900 300 L 50 50 1 1 B C
X PTD7\CMT_IRO\UART0_TX\FTM0_CH7\FTM0_FLT1 64 3900 2400 300 L 50 50 1 1 B
X VREFL 15 -2050 3000 300 D 50 50 1 1 B
X PTA3\JTAG_TMS\SWD_DIO\TSI0_CH4\UART0_RTS_b\FTM0_CH0 25 -3450 -2550 300 R 50 50 1 1 B
X PTB0\LLWU_P5\ADC0_SE8\ADC1_SE8\TSI0_CH0\I2C0_SCL\FTM1_CH0\FTM1_QD_PHA 35 3900 -1650 300 L 50 50 1 1 B
X PTC2\ADC0_SE4b\CMP1_IN0\TSI0_CH15\SPI0_PCS2\UART1_CTS_b\FTM0_CH1\FB_AD12\I2S0_TX_FS 45 3900 -150 300 L 50 50 1 1 B
X PTC10\ADC1_SE6b\I2C1_SCL\I2S0_RX_FS\FB_AD5 55 3900 1050 300 L 50 50 1 1 B
X VSSA 16 -50 -3000 300 U 50 50 1 1 W
X PTA4\LLWU_P3\NMI_b\EZP_CS_b\TSI0_CH5\FTM0_CH1 26 -3450 -50 300 R 50 50 1 1 B
X PTB1\ADC0_SE9\ADC1_SE9\TSI0_CH6\ADC0_SE9\ADC1_SE9\TSI0_CH6\PTB1 36 3900 -1500 300 L 50 50 1 1 B
X PTC3\LLWU_P7\CMP1_IN1\SPI0_PCS1\UART1_RX\FTM0_CH2\CLKOUT\I2S0_TX_BCLK 46 3900 0 300 L 50 50 1 1 O C
X PTC11\LLWU_P11\ADC1_SE7b\I2C1_SDA\I2S0_RXD1\FB_RW_b 56 3900 1200 300 L 50 50 1 1 B
X VREF_OUT\CMP1_IN5\CMP0_IN5\ADC1_SE18 17 3900 -2250 300 L 50 50 1 1 O
X PTA5\USB_CLKIN\FTM0_CH2\CMP2_OUT\I2S0_TX_BCLK\JTAG_TRST_b 27 3900 -1950 300 L 50 50 1 1 O C
X PTB2\ADC0_SE12\TSI0_CH7\ADC0_SE12\TSI0_CH7\PTB2 37 3900 -1350 300 L 50 50 1 1 B
X VSS 47 150 -3000 300 U 50 50 1 1 W
X PTD0\LLWU_P12\SPI0_PCS0\UART2_RTS_b\FB_ALE\FB_CS1_b\FB_TS_b 57 3900 1350 300 L 50 50 1 1 B
X DAC0_OUT\CMP1_IN3\ADC0_SE23 18 3900 -2100 300 L 50 50 1 1 O
X PTA12\CMP2_IN0\CAN0_TX\FTM1_CH0\I2S0_TXD0\FTM1_QD_PHA 28 -3450 -200 300 R 50 50 1 1 B
X PTB3\ADC0_SE13\TSI0_CH8\ADC0_SE13\TSI0_CH8\PTB3 38 3900 -1200 300 L 50 50 1 1 B
X VDD 48 -150 3000 300 D 50 50 1 1 W
X PTD1\ADC0_SE5b\SPI0_SCK\UART2_CTS_b\FB_CS0_b 58 3900 1500 300 L 50 50 1 1 B
X XTAL32 19 -3450 -1650 300 R 50 50 1 1 B
X PTA13\LLWU_P4\CMP2_IN1\CAN0_RX\FTM1_CH1\I2S0_TX_FS\FTM1_QD_PHB 29 -3450 -350 300 R 50 50 1 1 B
X PTB16\TSI0_CH9\UART0_RX\FB_AD17\EWM_IN 39 3900 -1050 300 L 50 50 1 1 B
X PTC4\LLWU_P8\SPI0_PCS0\UART1_TX\FTM0_CH3\FB_AD11\CMP1_OUT 49 3900 150 300 L 50 50 1 1 O
X PTD2\LLWU_P13\SPI0_SOUT\UART2_RX\FB_AD4 59 3900 1650 300 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
#End Library