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FinalProject.qsf
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173 lines (171 loc) · 9.82 KB
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 19:08:49 April 26, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# FinalProject_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C7G
set_global_assignment -name TOP_LEVEL_ENTITY FinalProject
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:08:49 APRIL 26, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_N14 -to clock
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clock
set_location_assignment PIN_V10 -to row1
set_location_assignment PIN_W10 -to row2
set_location_assignment PIN_V9 -to row3
set_location_assignment PIN_W9 -to row4
set_location_assignment PIN_AB3 -to column1
set_location_assignment PIN_Y3 -to column2
set_location_assignment PIN_AB2 -to column3
set_location_assignment PIN_AA2 -to column4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to column1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to column2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to column3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to column4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to row1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to row2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to row3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to row4
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to row1
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to row2
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to row3
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to row4
set_location_assignment PIN_C18 -to seg1[0]
set_location_assignment PIN_D18 -to seg1[1]
set_location_assignment PIN_E18 -to seg1[2]
set_location_assignment PIN_B16 -to seg1[3]
set_location_assignment PIN_A17 -to seg1[4]
set_location_assignment PIN_A18 -to seg1[5]
set_location_assignment PIN_B17 -to seg1[6]
set_location_assignment PIN_A16 -to seg1[7]
set_location_assignment PIN_B20 -to seg2[0]
set_location_assignment PIN_A20 -to seg2[1]
set_location_assignment PIN_B19 -to seg2[2]
set_location_assignment PIN_A21 -to seg2[3]
set_location_assignment PIN_B21 -to seg2[4]
set_location_assignment PIN_C22 -to seg2[5]
set_location_assignment PIN_B22 -to seg2[6]
set_location_assignment PIN_A19 -to seg2[7]
set_location_assignment PIN_F21 -to seg3[0]
set_location_assignment PIN_E22 -to seg3[1]
set_location_assignment PIN_E21 -to seg3[2]
set_location_assignment PIN_C19 -to seg3[3]
set_location_assignment PIN_C20 -to seg3[4]
set_location_assignment PIN_D19 -to seg3[5]
set_location_assignment PIN_E17 -to seg3[6]
set_location_assignment PIN_D22 -to seg3[7]
set_location_assignment PIN_F18 -to seg4[0]
set_location_assignment PIN_E20 -to seg4[1]
set_location_assignment PIN_E19 -to seg4[2]
set_location_assignment PIN_J18 -to seg4[3]
set_location_assignment PIN_H19 -to seg4[4]
set_location_assignment PIN_F19 -to seg4[5]
set_location_assignment PIN_F20 -to seg4[6]
set_location_assignment PIN_F17 -to seg4[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg1[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg1[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg1[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg1[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg1[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg1[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg1[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg1[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg2[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg2[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg2[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg2[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg2[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg2[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg2[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg2[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg3[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg3[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg3[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg3[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg3[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg3[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg3[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg3[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg4[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg4[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg4[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg4[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg4[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg4[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg4[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg4[0]
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH FinalProject_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME FinalProject_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id FinalProject_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME FinalProject_tb -section_id FinalProject_tb
set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/FinalProject_tb.v -section_id FinalProject_tb
set_global_assignment -name VERILOG_FILE FinalProject.v
set_global_assignment -name VERILOG_FILE fpa_adder.v
set_global_assignment -name VECTOR_WAVEFORM_FILE output_files/Waveform.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_location_assignment PIN_B8 -to pb
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to pb
set_location_assignment PIN_AB7 -to d1
set_location_assignment PIN_AB8 -to d2
set_location_assignment PIN_AB9 -to d3
set_location_assignment PIN_Y10 -to d4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to d1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to d2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to d3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to d4
set_location_assignment PIN_A8 -to led1
set_location_assignment PIN_A9 -to led2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led2
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top